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Published Articles by N. S. Murthy
- Title: An Efficient Delay Estimation Model for High Speed VLSI Interconnects
Authors: M. Kavicharan, N. S. Murthy, N. Bheema Rao
Doi: 10.37394/23204.2022.21.3
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Published in WSEAS Transactions on Communications, Volume 21, 2022 - Title: A Closed-form Delay Estimation Model for Current-mode High Speed VLSI Interconnects
Authors: M. Kavicharan, N. S. Murthy, N. Bheema Rao
Doi: 10.37394/23204.2021.20.26
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Published in WSEAS Transactions on Communications, Volume 20, 2021 - Title: Transient Analysis of VLSI Tree Interconnects Based on Matrix Pade Type Approximation
Authors: M. Kavicharan, N. S. Murthy, N. Bheema Rao
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Published in WSEAS Transactions on Circuits and Systems, Volume 13, 2014