WSEAS Transactions on Circuits and Systems
Print ISSN: 1109-2734, E-ISSN: 2224-266X
Volume 25, 2026
A Practical Methodology for Designing and Optimizing a Three-Stage Ring Oscillator in 180-nm CMOS Technology using Particle Swarm Optimization (PSO)
Authors: , , ,
Search Articles
Abstract: This paper presents the design and optimization of a three-stage ring Oscillator (RO) with enhanced performance in terms of phase noise and power consumption. The proposed design is implemented using TSMC 0.18 μm CMOS technology and operates at a central frequency of 2.93 GHz with a 5 V supply voltage. To address design challenges and achieve optimal performance, Particle Swarm Optimization (PSO) is employed to determine the optimal design parameters, targeting low phase noise, reduced power dissipation, and an improved figure of merit (FOM). The ring oscillator topology is implemented and simulated using the ADS tool. The obtained results demonstrate a phase noise of −117.667 dBc/Hz at 1 MHz offset, with a power consumption of only 7.25 mW, confirming the effectiveness of the proposed approach.
Keywords:
CMOS Ring oscillator, Phase noise, PSO, Metaheuristic, Optimization, Figure-of-merit (FOM), Power consumption
Pages: 281-287
DOI: 10.37394/23201.2026.25.25