Abstract: Compact instruction set architectures are essential for low-power embedded processors and educational CPU design, where hardware simplicity and code density are critical. Traditional RISC architectures such as MIPS and ARM employ wide instruction formats and large register files, which increase decoding complexity, silicon area, and power consumption. This paper presents AURORA-15, a fixed-length 15-bit instruction set architecture designed to achieve reduced hardware overhead while maintaining functional adequacy for embedded applications. The proposed ISA adopts a 28-bit datapath, an accumulator-influenced execution model, and a compact register file of eight registers, including dedicated zero, stack pointer, and link registers. Only two instruction formats are used to simplify decoding and control logic. PC-relative branching and base–offset addressing eliminate the need for complex absolute control hardware, while a partially reserved opcode space enables future extensibility. Functional validation using representative programs confirms correct arithmetic, memory, and control-flow operations. A comparative analysis with a MIPS-style architecture shows improved code density, reduced register file size, and lower decoder complexity. Owing to its minimal design and scalability, AURORA-15 is well suited for FPGA-based soft processors, educational platforms, and resource-constrained embedded systems.

Keywords: Instruction Set Architecture (ISA), Embedded Processors, Code Density, Accumulator-Based Architecture, Low-Power CPU Design, Compact Instruction Encoding, FPGA Soft-Core Processor

Pages: 40-53

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