WSEAS Transactions on Power Systems
Print ISSN: 1790-5060, E-ISSN: 2224-350X
Volume 17, 2022
Design of a Low-Power Low-Noise ECG Amplifier for Smart Wearable Devices Using 180nm CMOS Technology
Authors: , ,
Abstract: Wearable biomedical devices for recording electrocardiograms (ECG) are becoming more and more popular as they provide clinicians with a comprehensive view of a patient's diagnosis. ECG signals are characterized by low amplitude and are susceptible to many kinds of noise, so high gain and high common mode rejection ratio (CMRR) are essential to suppress them, while ultra-low power low noise (AFE) is used for Analog front-end for ECG signal acquisition, based on a Drive Right Leg (DRL) circuit that combines common-mode feedback with high CMRR and a notch filter band with a cutoff frequency of 50, implemented in CMOS 180 nm technology. According to the simulation results, this front-end circuit can yield a mid-band gain of 50.75 dB at -3dB bandwidth from 100mHz to 100 Hz, a Power Supply Rejection Ratio (PSRR) of 113 dB, and a Common Mode Rejection Ratio (CMRR) of 102 dB, exhibit an input-referred noise (IRN) of 1.47 μVrms from 0.1 Hz to 1kHz，corresponding to a noise efficiency factor (NEF) of 2.74. The AFE consumes 1.08 μW from the 1.8V supply voltage.
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Keywords: ECG, CMOS Amplifier, CMRR, IRN, DRL Circuit, Low-power, Low-noise, NEF, Power Line Interference
Pages: 177-186
DOI: 10.37394/232016.2022.17.18