WSEAS Transactions on Power Systems
Print ISSN: 1790-5060, E-ISSN: 2224-350X
Volume 15, 2020
Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications
Authors: , , , , ,
Abstract: This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any on-chip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 μm2. The regulator operates with supply voltages from 1.2V to 2V.
Search Articles
Keywords: Low-dropout linear regulators, CMOS analog integrated circuits, Weak inversion region, Power consumption, Negative and Positive feedback, Noise
Pages: 240-248
DOI: 10.37394/232016.2020.15.28