WSEAS Transactions on Electronics
Print ISSN: 1109-9445, E-ISSN: 2415-1513
Volume 15, 2024
Performance Augmentation, Parameter Modeling and Analysis of Nano-DG-TFET
Author:
Abstract: In this manuscript, we propose and analyze the properties of an efficient Nano strained-silicon dual-halo high-K dielectric stacked multi-material dual-gate TFET device (Nano-DG-TFET). Compact precise models for this projected Nano TFET are mathematically proposed for the electric field, surface potential, drain current and threshold voltage. Using gate and channel (G&C) engineering, the models are derived by solving the 2-D Poisson equation in silicon-graded channel region by applying suitable boundary conditions. The real-time values of the devices diverge due to various SCEs, second-order effects, and non-idealities present in the device. Hence, the proposed models incorporate the effects of various device parameters such as channel potential, electric field, DIBL, threshold voltage roll-off, and drain current. Also, the fringing capacitance characteristics of the proposed Nano-DG-TFET demonstrate superior performance over Triple Material Double Gate (TMDG) and Single Material Double Gate (SMDG) TFET structures. The proposed Nano-DG-TFET incorporates many other efficient device properties like strained silicon (s-Si) channel, halo implantation, high-K dielectric gate stack, triple material gate terminal, and many more. Therefore, it is evident that the proposed nanodevice structure provides poor outflow current IOFF $$(10^{−16}A/μm)$$, and remarkable betterment in ON current ION $$(10^{−6}A/μm)$$. The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes to validate the robustness of the model.
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Keywords: Dual-Gate TFET, Threshold Voltage, Dual-Halo, high-K Dielectric, Fringing capacitance, Strained Silicon, Short Channel Effects
Pages: 184-194
DOI: 10.37394/232017.2024.15.20