Performance Augmentation, Parameter Modeling and Analysis of

Nano-DG-TFET

YASHU SWAMI

Department of ECE,

Aditya Engineering College (A),

Surampalem 533437,

INDIA

device. Hence, the proposed models incorporate the effects of various device parameters such as channel

potential, electric field, DIBL, threshold voltage roll-off, and drain current. Also, the fringing capacitance

characteristics of the proposed Nano-DG-TFET demonstrate superior performance over Triple Material Double

Gate (TMDG) and Single Material Double Gate (SMDG) TFET structures. The proposed Nano-DG-TFET

incorporates many other efficient device properties like strained silicon (s-Si) channel, halo implantation, high-

K dielectric gate stack, triple material gate terminal, and many more. Therefore, it is evident that the proposed

nanodevice structure provides poor outflow current IOFF (10−16A/μm), and remarkable betterment in ON current

ION (10−6A/μm). The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at

various technology nodes to validate the robustness of the model.

1 Introduction

To augment the device performance and suppress

Short Channel Effects (SCE), we need to upgrade

the device structure and properties. An efficient

Nano strained-silicon dual-halo high-K dielectric

stacked multi-material dual-gate TFET device

(Nano-DG-TFET) is proposed with enhanced

properties. To improve the device carrier properties

we use Strained-Silicon (s-Si) material in designing

the device, [1], [2]. This improves the lattice

drive capability of the nanodevice, [3], [4].

Furthermore, because of this HCEs, the damaged

interface region extends from drain to source with

fixed charge density. A number of researchers have

investigated the fixed charge degradation in DG

TFETs, further stating that these localized charge

The tunneling gate region (auxiliary gate) is

partitioned from VDS beyond saturation because the

auxiliary gate ingests additional VDS, limiting the

SCEs. In the tunneling area, we used germanium as

the source material and intrinsic silicon as the

channel material, making a hetero-junction.

Furthermore, G&C engineering is also used in our

proposed Nano-DG-TFET to lower both SCEs and

HCEs, [8].

numerous analytical approaches for obtaining VTH

features of SOI and DG-TFETs, [9], [10]. The

analytical model of s-Si on Silicon-Germanium-on-

Insulator TFET, VTH and roll-off approach is

developed in [10]. Furthermore, the parameters of

effective gate oxide and channel were carefully

chosen to improve VTH and roll-off. Few research

works have developed a 2-D analytical modeling of

ambipolar characteristics for asymmetric TFETs,

how different front-gate and back-gate biases affect

the development of substrate bias, a significant

quantity of body impact coefficient causes large

variation in VTH, adding complexity to the circuit

design. Double halo doping has been used as a sort

of G&C engineering to manage these outcomes. A

compact model is proposed for fully depleted nano-

scale dual-halo high-K dielectric stacked Triple-

Material DG-TFET. The model formulation has

been mathematically proposed for the electric field,

surface potential, ID and VTH. The proposed

(15)

The built-in potential (Vbi) is represented as:

Halo doping concentration around the S-C and D-C

regions is symbolized by NDS and NAh respectively.

Substituting (17), (18) and (19) in surface potential

base equation (2), we get

characteristics. As a result, we will be able to

develop a robust model.

characteristic length value appears at the

intermediate channel region.

Hence, the channel potential in the intermediate

region can be expressed as:

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Using (32) in (29), the xmin can be simplified as:

The VTH condition has been determined using (33–

35):

In Appendix 2, the formulas for VTHL and K1 –

K8 are simplified.

The difference between the VTH short channel -

slanting angle in radians, and maximum internal

potential along the channel length (L). It is self-

evident that as VGS rises, the channel potential rises

as well. As a result, the S-C potential barrier

diminishes, increasing the ID as more carriers enter

the channel from the source. Furthermore, because

the S-C potential barrier is reduced as the strain in

the channel grows, the ID increases.

Fig. 6 (a) and (b): Lateral Electrical Field

distribution (Ex) and Vertical Electric Field

distribution (Ey) in the proposed Nano-DG-TFET

channel for VGS = 0.1V and VDG = 0.5V

between the D-C and S-C region, the lateral electric

along the channel, the alteration in the electric field

for proposed Nano-DG-TFET, SMDG-TFET, and

TMDG-TFET is shown in Figure 7.

with VGS = 0.1V and VDS = 0.5V). The S-C built-in

potential is evidently enhanced by lowering the tox

and silicon thickness, allowing the gate to exert

greater influence over the channel than the drain,

lowering the SCEs.

Fig. 9: VTH roll-off vs. L, comparison plot for the

proposed Nano-DG-TFET, SMDG-TFET, TMDG-

TFET with VGS = 0.1V, VDS = 0.05V

considered TFET devices for comparison. For L

below 10 nm, the roll-off for the Nano-DG-TFET

structure is lower than SMDG-TFET and TMDG-

TFET structures. Hence this SCE is lowest for the

proposed Nano-DG-TFET. Figure 10 shows the VTH

Fig. 10: VTH roll-off vs. L of the proposed Nano-DG-

as shown in the graph. The variations of the VDS vs.

can observe that the upsurge in ID with VGS is due to

the decrease in the S-C barrier distance.

Fig. 13: (a) VTC of the proposed Nano-DG-TFET

for different dielectrics at VDS = 1V. (b) Output

characteristics of the proposed device for different

gate bias values

plot represents the device characteristics, and how

effective the device is at restraining ambipolarity. In

comparison to SM and TM equivalent structures, the

device considered displays increased ION and

minimal ambipolar conduction by choosing the

correct materials for S-C gate sides and D-C gate

sides. The accuracy of our ID model is confirmed by