K. K. Nagarajan, N. Vinodhkumar, R. Srinivasan, "Optimization of Gate - Source/Drain Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations," WSEAS Transactions on Circuits and Systems, vol. 11, pp. -, 2012, DOI:
K. K. Nagarajan, N. Vinodhkumar, R. Srinivasan. Optimization of Gate - Source/Drain Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations.
WSEAS Transactions on Circuits and Systems. 2012;11:-.
WSEAS Transactions on Circuits and Systems
Print ISSN: 1109-2734, E-ISSN: 2224-266X
Volume 11, 2012
Optimization of Gate - Source/Drain Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations
Authors: , ,
Abstract: The effect of gate – drain/source underlap (Lun) on a narrow band LNA performance has been studied, in 30 nm FinFET using device and mixed mode simulations. Studies are sssssdone by maintaining and not maintaining the leakage current (Ioff) and threshold voltage (Vth) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used as performance metrics. To get the better noise performance and gain, Lun in the range of 3-5nm is recommended.
Pages: - WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 11, 2012DOI: *As the DOI is a unique identifier, it is already available in the pdf version.
**The DOI link will be activated in the first midst of January 2026.
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