WSEAS Transactions on Systems
Print ISSN: 1109-2777, E-ISSN: 2224-2678
Volume 12, 2013
New Approach to Memory Less Design and Look-Up-Table Realization for Low-Complexity Reconfigurable Digital FIR Filter Architectures
Authors: ,
Abstract: Low-complexity and high-speed digital finite impulse response (FIR) filter is widely used in various signal processing and image processing applications because of less area, low cost, low power and high speed of operation. This article presents optimum low-complexity, reconfigurable digital FIR filter architectures based on memory less design and look up table (LUT) realization. The memory less design uses computation sharing multipliers (CSHM) and binary based common sub-expression elimination (BCSE) method for different word length filter coefficients. The memory based LUT multiplier approach uses memory elements to store the sub set of products of the filter coefficients. The LUT based multiplier removes the need of decoders in the FIR filter design. Thus reduce hardware complexity of the proposed reconfigurable digital FIR filter architectures. In this article, we show that the proposed memory based LUT multiplier approach could be an area-efficient alternative to distributed arithmetic (DA) based design of FIR filter with the same throughput of implementation. Also the proposed novel reconfigurable FIR filter architecture using CSHM involves less area and lower latency of implementation compared to the existing reconfigurable FIR filter implementations.
Search Articles
Keywords: Memory-based computing, Common sub-expression elimination (CSE), Low-complexity, Reconfigurable architectures, VLSI