Abstract: Signals are converted, processed and transmitted digitally exploiting the limitations of the sensory organs of humans, approximating their speech, image and videos but the real world is analog. Interfacing analog and digital systems is necessary to fully leverage the power of digital computation. Design of power-efficient, high sampling rate, noise resistant analog to digital converters (ADCs) remains a significant hurdle in analog circuit design. This paper offers a ready reference to researchers investigating recent developments in time interleaved successive approximation register (TI-SAR) ADC circuit design. Over 20 publications were analysed, extracting valuable and innovative features of the circuits and presenting it in a concise manner. The paper aims to address the lack of comprehensive review articles regarding advancements in time interleaved SAR ADC circuit design. Along with circuit level innovations, the paper also discusses the challenges involved in designing high speed TI-SAR ADCs. The calibration issues, effects of mismatch and reduction of settling time are the bottlenecks with reference to speed. Investigation of the problems and possible solutions combining techniques from multiple papers have been qualitatively summarized. The article guarantees equitable/unbiased comparison of different performance metrics of ADCs such as sampling rate, power consumption, area, SNDR (signal to noise and distortion ratio), figure of merit and process.

Keywords: analog-to-digital converter (ADC), time-interleaved, successive approximation register, calibration, mismatch, sampling rate, high-speed

Pages: 267-276

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