Abstract: This paper presents a design methodology for a 2.6 GHz CMOS LC Voltage-Controlled Oscillator (VCO) using the AMS 0.35 μm CMOS process. The approach focuses on minimizing power consumption, reducing phase noise, and maximizing the figure-of-merit (FOM). To overcome the complex trade-offs in analog design, a metaheuristic Particle Swarm Optimization (PSO) algorithm is employed to determine the optimal dimensions of the MOS transistors. The PSO targets the reduction of phase noise while respecting technological and performance constraints. The proposed VCO is simulated using ADS, showing a phase noise of –125.35 dBc/Hz at 1 MHz offset and a power consumption of 9 mW. A comparative study with existing designs highlights the advantages of the proposed method, demonstrating improved performance in terms of phase noise and FOM. These results confirm the effectiveness of the optimization-based design approach for high-performance RF VCOs in CMOS technology.

Keywords: VCO, Metaheuristic, Optimization, PSO, CMOS LC-VCO, Double cross-coupled transistors, Tuning range, Phase noise, figure-of-merit (FOM)

Pages: 143-149