Abstract: This paper describes the design and implementation of a 9-tap Finite Impulse Response (FIR) filter using the Vivado Design Suite. The filter is intended for real-time noise reduction and signal smoothing in embedded systems. FIR filters are naturally stable and well-suited for applications that require a linear phase response. Vivado’s IP-centric development environment, along with its high-level synthesis and simulation tools, offers flexibility in filter customization, effective testing, and reliable deployment on FPGAs. A testbench was created to evaluate the filter’s performance using synthesized sine waves with mixed frequencies. The design incorporates pipelining to reduce latency and boost throughput. Results show that high-frequency noise is effectively suppressed while preserving the target signals. This approach can also be scaled to support 2D and 3D filtering, making it a strong fit for advanced signal processing in embedded applications.

Keywords: FIR Filter Design, Vivado Design Suite, FPGA Implementation, Digital Signal Processing, Pipelined Architecture, HDL, Fixed-Point Arithmetic, Real-Time Filtering, Embedded Systems

Pages: 122-130