WSEAS Transactions on Signal Processing
Print ISSN: 1790-5052, E-ISSN: 2224-3488
Volume 13, 2017
Comparative Analysis of Two Op-Amp Topologies for a 40MS/s 8-bit Pipelined ADC in 0.18µm CMOS Technology
Authors: ,
Abstract: The performances of two full differential operational amplifiers (Op-Amps) telescopic and folded-cascode are evaluated to satisfy the stringent requirements on the amplifier to be used in a Multiplying Digital-to-Analog Converter (MDAC) stage of a pipelined ADC (Analog-to-Digital Converter). The paper shows the solutions found to reach high gain, wide bandwidth and short settling time without degrading too much the output swing. The Op-Amp specifications are extracted according to the ADC requirements, then the two Op-Amp topologies are designed, tested and their performances are compared. Simulation results show that the Op-Amp folded-cascode topology is more suitable architecture for pipelined ADC than the telescopic one. Moreover, the use of this type of Op-Amp generates an Integral Non-Linearity (INL) error less than that of the telescopic one. The analyses and simulation results are obtained using 0.18 µm AMS (Austria Mikro System) CMOS process parameters with a power supply voltage of 1.8V. The predicted performance is verified by analysis and simulations using Cadence EDA simulator.
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Keywords: CMOS analog circuit design, Op-Amp, Multiplying Digital-to-Analog Converter, pipelined ADC
Pages: 83-89
WSEAS Transactions on Signal Processing, ISSN / E-ISSN: 1790-5052 / 2224-3488, Volume 13, 2017, Art. #10