WSEAS Transactions on Electronics
Print ISSN: 1109-9445, E-ISSN: 2415-1513
Volume 15, 2024
Physical Design Implementation to Enhance Performance of Ultra-Deep Sub-micron (UDSM) Hard Macro-based Design
Authors: , , ,
Abstract: Lower technology nodes or Ultra Deep Sub-micron (UDSM) used in today’s System on-chip (SoC) yield high performance and are faster when compared to the Deep Sub-micron (DSM) technology nodes. The challenges faced by a designer have increased multi-fold in SoC design with the technology node evolution. The designs that are trending these days are Hard Macro (HM) based designs. The entire block is divided in the sub- HMs or hierarchical blocks. The sub-HM layout shapes are decided during the partitioning of the top-level block. Each of the hierarchical blocks is implemented separately and the sub-HMs are integrated at the top level to reduce the huge run-time and to reduce the burden of improving the PPA. The processes involved in Physical Design (PD) are interlinked and the effect of the previous process can be seen in the subsequent stages. CTS is implemented using Flexible-H-tree (FHT) with Multiple tap point structure. Experimental results on an industrial design having more than a million instances show that the implementation of the proposed clock tree structure comprising of FHT with Multitap point CTS (DB2), in the design, shows huge improvement in terms of timing and clock metrics when compared to the conventional CTS (DB1). A reduction of 40.47% and 63.9% is seen in terms of hold WNS and hold TNS respectively from DB1 to DB2. The NFE is reduced by 27.33% from DB1 to DB2. DB2 has a clock latency of 1.073 ns which is 27% lesser than that of DB1. Global Skew is reduced by 15.48% and local skew by 20%. Innovus tool is used for the implementation of the design.
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Keywords: Ultra Deep Sub-micron (UDSM), Physical Design, Multi-Tap point CTS, MSCTS, Flexible h-tree, Hard Macro design
Pages: 88-96
DOI: 10.37394/232017.2024.15.11