International Journal of Electrical Engineering and Computer Science
E-ISSN: 2769-2507
Volume 6, 2024
A Review Paper on Memory Fault Models and its Algorithms
Authors: , , ,
Abstract: The significance of testing semiconductor memories has grown significantly in the semiconductor industry due to the increased density of modern memory chips. This paper aims to investigate and analyze
different types of functional faults present in today's memory technology. These faults include stuck-at faults,
transition faults, coupling faults, address decoder faults, and neighborhood pattern-sensitive faults. The paper also delves into the techniques utilized to identify and detect these faults. In particular, the focus is placed on the importance of zero-one, checkerboard, and March pattern tests, which are widely employed to assess functional memory defects at different levels, such as the chip level, array level, and board level. Furthermore,
the study provides an in-depth exploration of various test algorithms and thoroughly examines their fault
coverage capabilities. Overall, this review paper provides valuable insights into the challenges posed by the
dense nature of modern memory chips and offers a comprehensive analysis of functional faults in memory technology. By emphasizing the importance of testing and presenting a detailed exploration of fault detection
methods and test algorithms, this study contributes to the advancement of reliable and high-performance memory devices in the electronic industry suggesting that MARCH algorithms outperform others when considering factors like fault coverage, power efficiency, area optimization, and time complexity parameters, making them the preferable choice for reliable and high-performance memory devices in the electronic industry.
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Keywords: Memory Faults, Memory Test Algorithms, BIST (Built in Self-Test), Memory array, March test, MATS, Up Transition, Down Transition, MSCAN, DFT, Fault coverage
Pages: 143-151
DOI: 10.37394/232027.2024.6.17