WSEAS Transactions on Systems and Control
Print ISSN: 1991-8763, E-ISSN: 2224-2856
Volume 17, 2022
Design and Performance Analysis of Memristor and IMPLY Adder based 64-bit Vedic Multiplier and CAM Memory with Gbps throughput on FPGA
Authors: , ,
Abstract: Memristors are a new area with various intriguing properties that make them useful for both storage and computing. We propose a semi-serial IMPLY-based adder that uses Memristor to design high speed and high throughput with minimal latency 64-bit Vedic multiplier and provide a detailed study of its benefits and proposed system focuses on the design of Content Addressable Memory. A fundamental property of the given adder, in comparison to state-of-the-art adders, is its simplicity. Based on a quality factor that gives the series of steps and the requisite die area equal weight researchers indicate that the suggested multiplier outperforms prior attempts. The proposed system is validated using key metrics including Figures of Merit, and detailed comparison analyses are carried out to better understand centered mathematical entities, their features, strategy aspects, and benefits and downsides when equated. This makes it easier for scientists in charge of layout and investigators in the field to create, or select, appropriate units. Domain-specific logic circuits based on memristors may conduct logic operations and store logic values, providing an attractive prospect for the creation of complex intellectual architectures. A novel stateful logic implementation based on memristors has been proposed in this paper. Single-input NOT and COPY operations and multi-input AND, OR, NAND, NOR, and CAM memory manipulations are all possible with the proposed technique. Non-volatile memristor resistances are employed as output and input states in each logic gate, allowing stateful logic operations to be performed. When compared to other methods, the suggested method can result in a multi-functional stateful logic circuit that can conduct many stateful logic operations at the same time. The effectiveness of the proposed design is illustrated using MATLAB to verify the basic characteristics of Memristor and synthesized in Vivado Design Suite 2018.1 platform and compared with theoretical calculations. Based on obtained outcomes in terms of hardware utilization and speed, throughput, and latency, 11% improvement in throughput, 31% improvement in speed, 9% in latency, and a 15% reduction in area.
Search Articles
Keywords: Gates IMPLY based Adder, 64-bit Vedic Multiplier, CAM, FoM, Memristor, FPGA, and Clock gated techniques
Pages: 368-378
DOI: 10.37394/23203.2022.17.41