WSEAS Transactions on Computers
Print ISSN: 1109-2750, E-ISSN: 2224-2872
Volume 11, 2012
The ChipCflow Project to Accelerate Algorithms using a Dataflow Graph in a Reconfigurable System
Authors: , , ,
Abstract: In this paper, the ChipCflow Project to accelerate algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is presented. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates. The results of benchmarks implemented using the static dataflow architecture are reported at the end of this paper.