WSEAS Transactions on Circuits and Systems
Print ISSN: 1109-2734, E-ISSN: 2224-266X
Volume 11, 2012
Advanced Design of TQ/IQT Component for H.264/AVC Based on SoPC Validation
Authors: , , ,
Abstract: This paper presents an advanced hardware architecture for integer transform, quantization, inverse quantization and inverse integer transform modules dedicated to the macroblock engine of the H.264/AVC video codec standard. Our highly parallel and pipelined architecture is designed to be used for intra and inter prediction modes in H.264/AVC. The TQ/IQT design is described in VHDL language and synthesized to Altera Stratix II FPGA and to TSMC 0.18μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 1070 millions of pixels per second at 171.4 MHz when mapped to standard-cells. In addition, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded Altera development board.