WSEAS Transactions on Communications
Print ISSN: 1109-2742, E-ISSN: 2224-2864
Volume 12, 2013
Efficient Hardware Implementation of Advanced Soft Information-Set Decoders in FPGAs
Authors: , , , ,
Abstract: This paper has four main goals: (i) to describe in detail a new architecture to implement soft-decision, information-set-based decoders purely in hardware; (ii) to investigate the effects of quantization of the received word on the decoder performance, calculating the minimum number of bits that should be adopted; (iii) to present a strategy for optimizing the choice of candidate codewords, allowing the selection of a small set with a very high probability of containing the best candidate; and (iv) to present a new acceptance criterion that is both highly efficient and well-suited for hardware implementations.The proposed architecture can be used to implement any linear block decoder and is shown to be highly area-efficient, with the C(48,24,12) code occupying only 20% of the smallest FPGA in the Stratix IV family. It is also shown that there is very little to gain by using more than 3 quantization bits, and that sets as small as 3% of all possible values suffice to obtain essentially the same results as true MLD. The presented acceptance criterion reduces in 96.8% the number of candidates that must be evaluated for the C(24,12,8) code, with performance difference relative to the Taipale-Pursley criterion never larger than 12%.