WSEAS Transactions on Circuits and Systems
Print ISSN: 1109-2734, E-ISSN: 2224-266X
Volume 12, 2013
Performance Analysis of Novel Domino XNOR Gate in Sub 45nm CMOS Technology
Authors: , ,
Abstract: In this paper, three new versions of domino XNOR gate circuits are proposed. The proposed circuits adopt mixed N and P type transistor in the pull-down network. All performance parameters are measured at 25°C and 110°C. In first proposed circuit, it lowers the total leakage power by 8% to 12%, PDP is reduced by 6% to 9% and A.C noise margin is enhanced by 7% as compared to standard n-type XNOR gate. Second proposed circuit having multiple threshold voltage, lowers the total leakage power by 47% to 57%, PDP is reduced by 80% to 86%, and A.C noise margin is enhanced by 33% as compared to standard n-type XNOR gate. Third proposed circuit having multiple power supply, lowers the total power consumption by 56% to 65%, PDP is reduced by 83% to 88% and A.C noise margin is enhanced by 58% as compared to standard ntype XNOR gate.
Search Articles
Keywords: domino logic, gate oxide leakage current, noise margin, multiple threshold voltage, subthreshold leakage current, XNOR gate