WSEAS Transactions on Circuits and Systems
Print ISSN: 1109-2734, E-ISSN: 2224-266X
Volume 12, 2013
A Methodology for Placement-Aware Partitioning
Authors: , , , ,
Abstract: Circuit partition is the first stage of physical design. As the improvement of semiconductor technique, the number of transistors increases rapidly in a VLSI design. Therefore, how to partition a circuit effectively in order to reduce the design complexity becomes a crucial problem. In this paper, we propose a placement-aware partition methodology to reduce the total wire length after cell placement and global routing. A 2-way partitioning algorithm developed previously has been proved to be effective for the 3D IC partition problem. By the application of 2-way partitioning algorithm and a set of terminal propagation rules proposed in this paper, we can take into account the external interconnections of the target partition region effectively, and calculate the gain of partition precisely, such that the wire length could be minimized. A set of benchmarks from the 2011 ISPD contest are used to test our methodology. Experimental results show that in comparison with previous work, our methodology reduces the total wire length after placement in terms of both HPWL and STWL, and also reduces the real length of routing wires after global routing effectively.