WSEAS Transactions on Circuits and Systems
Print ISSN: 1109-2734, E-ISSN: 2224-266X
Volume 13, 2014
Low Space Complexity, High performance Unified and Scalable Word-Based Radix 4 Architecture for Montgomery Modular Multiplication in GF(P) and GF(2k)
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Abstract: This paper presents a novel low space complexity and high performance (low power and high speed) unified and scalable word-based radix 4 architecture for Montgomery modular multiplication in GF(P) and GF(2k). In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architectures extracted by L. Tawalbeh, and also the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. To reduce multiplier area and accelerate its operation, the hardware architecture employs 3-to-2 carry save adders instead of 4-to-2 carry save adder, as used in conventional designs, to avoid carry propagation at each addition operation of the add-shift loop. To reduce power consumption, glitch blockers are employed at the outputs of some circuit modules to reduce the spurious transitions and the expected switching activities of high fan-out signals. Moreover, the architecture was modified to reduce more power by replacing the dual field conventional 3-to-2 carry save adder (CSA) by modified low power dual field 3-to-2 CSA that has internal logic structure with balanced delays in SUM and CARRY outputs to reduce the chance of glitches occurrence. An ASIC Implementation of the proposed architecture shows that it can perform 1024-bit modular multiplication (for word size w = 32) in about 4.81 μs. Also, the results show that it has smaller Area x Time values compared to existing competing designs by ratios ranging from 13.1% to 77.2% which makes it suitable for implementation where both area and performance are of concern. Also, it has higher throughput over them by ratios ranging from 2.6% to 82.9%. In addition, it achieves a decrease in power consumption compared to these designs by ratios ranging from 25.3% to 70.4%.
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Keywords: Montgomery Modular Multiplier, Cryptography, Systolic Arrays, ASIC Design, Hardware Security
Pages: 429-439
WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 13, 2014, Art. #46