On the Design of Time-Predictable Low-Leakage Cache Memory for Real-Time Embedded Systems

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Abstract: This paper presents a multidisciplinary study that aims at designing a time-predictable low-leakage cache memory for real-time embedded systems. Both state-preserving and state-destroying leakage-saving mechanisms have been tested on a superscalar processor with two-level cache hierarchy. Full system simulation has been used to examine leakage-saving capability of each mechanism. In addition, a statistical approach has been proposed to study processor’s time-predictability under potential leakage-saving techniques. Furthermore, the performance of real-time embedded systems in presence of leakage-saving techniques has been thoroughly analyzed using Matlab/Simulink-based models. Each possible design alternative has been evaluated in terms of four parameters that include: average power saving, degree of predictability (DoP), loss of schedulability (LoS) and performance of the underlying embedded system. Our results have shown that applying a state-preserving leakage-saving mechanism on either first-level data cache or last-level unified cache provides the most viable design option. The first alternative has achieved an average power saving of 32.61 %, a DoP of 93.05% and a LoS of 0% while the second alternative has achieved an average power saving of 50.21%, a DoP of 80.30% and a LoS of 13.68%. Moreover, neither of them has caused any disruption in the performance of the experimental embedded system models. Consequently, using a first-level data cache with a state-preserving leakage-saving mechanism represents the best feasible option for systems with very critical timing requirements while employing a state-preserving low-leakage last-level cache can be the suitable option for systems with soft timing requirements and stringent power constrains.

WSEAS Transactions on Information Science and Applications, ISSN / E-ISSN: 1790-0832 / 2224-3402, Volume 12, 2015, Art. #9

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Mutaz Al-Tarawneh, "On the Design of Time-Predictable Low-Leakage Cache Memory for Real-Time Embedded Systems," WSEAS Transactions on Information Science and Applications, vol. 12, pp. 82-111, 2015, DOI:
Mutaz Al-Tarawneh. On the Design of Time-Predictable Low-Leakage Cache Memory for Real-Time Embedded Systems. WSEAS Transactions on Information Science and Applications. 2015;12:82-111.
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