WSEAS Transactions on Circuits and Systems
Print ISSN: 1109-2734, E-ISSN: 2224-266X
Volume 17, 2018
Two Stage Op-Amp Design Verification and Optimization by Symbolic Computation
Author:
Abstract: In the classical Op-Amp design some very simple expressions are used, based on a simplified circuit model. This could lead to a prototype whose response is not the desired one and the Op-Amp must be redesigned. Another possible case is when the designed Op-Amp’s response is the desired one but only for a certain load, a different load could produce an undesirable behavior or an unstable response. In this paper a two stage Miller compensated Op-Amp, designed in 180nm CMOS technology is verified from the point of view of phase margin and is optimized from the settling time point of view. To this aim the phase margin symbolic expression of the Op-Amp in the open loop is computed starting from poles and zeros symbolic expressions. Using this expression, an analysis to evaluate the influence of the Miller and the load capacitance on phase margin is performed. This way, the designer can rapidly verify if the response of the Op-Amp is stable for various Miller and load capacitances. After that the symbolic expression of the time constant is estimated starting from the poles and zeros symbolic expressions of the Op-Amp in the closed loop, function of the Miller and load capacitances. The settling time is evaluated for various Miller and load capacitances values to find the optimum, smallest time response. The numerical results for phase margin and settling time obtained with this algorithm are compared with those computed with SPECTRE RF.
Search Articles
Keywords: Op-Amp, pole/zero, phase margin, settling time, symbolic expressions, design verification, design optimization
Pages: 180-186
WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 17, 2018, Art. #22