Supervisory Controller Design to Enforce Boundedness,
Reversibility and Liveness in Systems Modeled by Timed Petri
Nets
ALTU ˘
G˙
IFTAR
Department of Electrical and Electronics Engineering
Eskis¸ehir Technical University
26555 Eskis¸ehir, TURKEY
Abstract: - Supervisory controller design to enforce boundedness, reversibility, and liveness in discrete-event
systems modeled by timed Petri nets where both transitions and places are timed is considered. A controller
design approach which uses the approach of stretching is proposed. The approach produces a supervisory
controller which guarantees boundedness and reversibility simultaneously. The designed controller also
guarantees T-liveness for the largest possible subset Tof the set of transitions. Therefore, boundedness,
reversibility, and liveness are enforced simultaneously whenever possible. Furthermore, the designed controller
is maximally permissive in the sense that no transitions are disabled unnecessarily and the reachability set
of the controlled system is the largest possible set in which boundedness and reversibility can be enforced
simultaneously. Controller design for an automated manufacturing system example is also presented to
demonstrate the proposed approach.
Key-Words: - Discrete Event Systems, Timed Petri Nets, Supervisory Control, Algorithms, Manufacturing
Systems, Robotic and Automation Systems
Received: November 17, 2022. Revised: August 23, 2023. Accepted: September 25, 2023. Published: October 16, 2023.
1 Introduction
Discrete-event systems (DES) are very common in
manufacturing, robotics, and automation systems.
A common formalism to model such systems is
Petri nets, [1], [2]. Although Petri nets were first
introduced without the notion of time, time may
play an important role in many DES. Thus, timed
Petri nets (TPNs) were introduced to describe the
evolution of these systems throughout time, [3], [4],
[5], [6], [7], [8], [9]. A TPN, unlike an untimed Petri
net, includes some time-delays, which are usually
associated with either transitions or places. A Petri
net in which time-delays are associated with tran-
sitions is commonly called a timed-transition Petri
net (TTPN) and a Petri net in which time-delays are
associated with places is commonly called a timed-
place Petri net (TPPN). The transitions and places
in a Petri net usually represent events and resources,
respectively. Therefore, when an event takes a cer-
tain time, it is natural to associate this time-delay
with the transition which represents that event. On
the other hand, when the use of a resource takes a
certain time, the time-delay must be associated with
the place which represents that resource. Therefore,
in a system in which both events and use of resources
take time, it may be necessary to use a TPN model,
where both transitions and places are timed.
To design a controller for any system, represen-
tation of the state of the system is, in general, nec-
essary. The state of an untimed Petri net can easily
be represented by the marking vector. However, the
representation of the state of a TPN is much more
complicated, [10]. To overcome this difficulty, the
method of stretching was first introduced for TTPNs
in [11], and then for TPPNs in [12]. The case of
TPNs where both transitions and places are timed
was then considered in [13].
In the present work, as in [11], [12], [13], it is
assumed that all the time-delays are commensurate;
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i.e., they are an integer multiple of a common
divisor. This assumption is justified since in many
practical systems a suitable time unit can be found
which divides (at least approximately) all the process
delays. Therefore, in this work, this unit is taken
as the unit of time and all the time-delays are thus
represented by an integer. Furthermore, the time
variable is also represented by an integer and is
denoted by k. Moreover, without loss of generality,
the initial time is assumed to be k= 0.
Since in any manufacturing and/or automation
system, any task requires a minimum time to com-
plete, in this work it is assumed that every transition
has a positive time-delay. On the other hand, since
some of the resources may become immediately
available, some of the places may have zero time-
delay.
Supervisory control is, in general, necessary for
DES to avoid undesirable behaviour, such as dead-
lock, [14], or to enforce desirable behaviour, such
as boundedness, reversibility, and/or liveness, [15].
Controller design to avoid deadlock in TTPNs and
TPPNs were respectively considered in [16], and
in [17], and to enforce boundedness, reversibility,
and liveness in TTPNs and TPPNs were respectively
considered in [18], and in [19]. Deadlock avoidance
controller design for TPNs in which both transitions
and places are timed was then considered in [13]. In
the present work, we consider supervisory controller
design to enforce boundedness, reversibility, and
liveness in TPNs in which both transitions and places
are timed.
Throughout the paper, we use Nand N+to
denote the sets of natural numbers (with zero) and
positive integers, respectively. For two vectors, aand
b, of the same dimension, a≥b(a≤b) means that
each element of ais greater (less) than or equal to
the corresponding element of b. For any vector a,
aTdenotes its transpose. For a set S,|S|denotes
the number of elements of Sand [S]idenotes the
ith element of S(i= 1,...,|S|).
2 Preliminaries
2.1 Timed Petri Nets
A TPN is a tuple G= (P, T, N, O, M0,DP,DT),
where Pis the set of places, Tis the set of
transitions, N:P×T→Nis the input matrix
that specifies the weights of arcs from places to
transitions, O:P×T→Nis the output matrix
that specifies the weights of arcs from transitions to
places, M0:P→Nis the initial marking vector
which specifies the number of tokens at each place
at the initial time k= 0,DP:P→Nis the vector
of the time-delays of the places, and DT:T→N+
is the vector of the time-delays of the transitions.
Graphically, a TPN can be represented as in
Fig. 1, where circles represent the places, bars rep-
resent the transitions, and the arrows represent the
arcs. An integer next to an arc indicates the weight of
that arc, an integer next to a place indicates the time-
delay of that place, and an integer next to a transition
indicates the time-delay of that transition. However,
to keep the graphics simple, when an arc has a unit
weight, we do not write its weight. Also, an arc with
a zero weight is not shown at all. Similarly, when a
place has a zero time-delay, or when a transition has
a unit time-delay, we do not write those. The dots
inside the circles indicate the tokens present in the
corresponding place at the initial time. Therefore,
for the example TPN shown in Fig. 1, we have
P={p1, p2, p3},T={t1, t2, t3},
N=
1 1 0
0 0 1
0 0 1
, O =
002
100
010
,
M0=
2
0
0
,DP=
1
1
0
,DT=
2
3
1
.
In a TPN, a token which enters a place p∈Pat
time kcan be used to enable a downstream transition
no earlier than at time k+DP(p). A transition t∈T
can fire at time konly if it is enabled at time k.
The transition t∈Tis enabled at time konly if
M(k)≥N(t), where M(k)denotes the number
of tokens at each place p∈Pat time k, which
entered place pat time k− DP(p)or earlier, and
N(t)denotes the column of Nwhich corresponds to
transition t. When a transition t∈Tfires at time k,
it withdraws N(p, t)tokens from each place p∈P
at time kand introduces O(p, t)tokens to each place
p∈Pat time k+DT(t), where N(p, t)and O(p, t)
are the elements of, respectively, Nand O, which
correspond to place pand transition t.
2.2 Stretched Petri Nets
The method of stretching for TPNs in which both
transitions and places are timed was introduced in
[13], to represent the state of such a TPN efficiently.
In this method, given a TPN, another TPN, called the
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• •
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@@@
@R
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?
p1
t1
p2
t2
p3
t3
1
2
1
3
2
Fig. 1. Example TPN, [13].
stretched Petri net (SPN) is first defined. The SPN
has, in general, more places and more transitions
than the original TPN. However, each place of the
SPN has zero time-delay and each transition has a
unit time-delay. To obtain the SPN, P1:= {p∈
P| DP(p)=0},P2:= {p∈P| DP(p)≥1},
T1:= {t∈T| DT(t)=1}, and T2:= {t∈
T| DT(t)≥2}are first defined. Then,
I) for any p∈P2,
i) DP(p)new places, pp
1,pp
2,. . .,pp
DP(p), and
DP(p)new transitions, tp
1,tp
2,. . .,tp
D(p)
are defined. Each new place is assigned
zero time-delay. The time-delay of pis also
redefined as zero. Furthermore, the newly
introduced transitions are such that each of
them has a unit time-delay and any one
of them fires immediately as it becomes
enabled.
ii) all the arcs which leave place pare de-
tached from p; instead, the originating end
of these arcs are attached to place pp
DP(p).
Furthermore, new arcs with unity weights
from pto tp
1, from tp
1to pp
1, from pp
1
to tp
2,. . ., and from tp
D(p)to pp
DP(p)are
introduced.
iii) the tokens inside place p(which indicate
the initial marking) are moved to place
pp
DP(p).
II) for any t∈T2,
i) DT(t)−1new places, pt
1,pt
2,. . .,pt
DT(t)−1,
and DT(t)−1new transitions, tt
1,tt
2,. . .,
tt
DT(t)−1are defined. Each new place is
assigned zero time-delay and each new
transition is assigned unit time-delay. The
?
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• •
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@@@
@R
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?
?
?
?
?
?
p1
tp1
1
pp1
1
t1
pt1
1
tt1
1
p2
tp2
1
pp2
1
t2
pt2
1
tt2
1
pt2
2
tt2
2
p3
t3
2
Fig. 2. SPN for the Example TPN, [13].
time-delay of tis also redefined as unity.
Furthermore, the newly introduced transi-
tions are such that any one of them fires
immediately as it becomes enabled.
ii) all the arcs which leave transition tare
detached from t; instead, the originating
end of these arcs are attached to transition
tt
DT(t)−1. Furthermore, new arcs with unity
weights from tto pt
1, from pt
1to tt
1, from
tt
1to pt
2,. . ., and from pt
DT(t)−1to tt
DT(t)−1
are introduced.
As a result of this procedure, the SPN shown in
Fig. 2 is obtained for the example TPN shown in
Fig. 1. The SPN can be defined as a tuple ˆ
G=
(ˆ
P , ˆ
T , ˆ
N, ˆ
O, ˆ
M0). Here, ˆ
P:= P∪Pnis the set
of places, where Pnis the set of newly introduced
places; ˆ
T:= T∪Tnis the set of transitions, where
Tnis the set of newly introduced transitions; ˆ
N:ˆ
P×
ˆ
T→Nand ˆ
O:ˆ
P׈
T→Nare, respectively, the
input and the output matrices; and ˆ
M0:ˆ
P→Nis
the initial marking vector. Since all the places of the
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SPN are delay-free and all the transitions have unit
time-delays, there is no need to include any vectors
to indicate the time-delays in the SPN definition ˆ
G.
We refer the reader to [13], for further details.
Although the SPN has, in general, more places
and transitions than the original TPN, its state at any
time k∈Nis solely and uniquely represented by
the marking vector ˆ
M(k)at time k. Furthermore, the
state of the SPN can be used to define the state of the
original TPN. Moreover, starting with ˆ
M(0) = ˆ
M0,
the evolution of the state of the SPN can easily be
described by the equation
ˆ
M(k+ 1) = ˆ
M(k) + X
t∈φ(k)hˆ
O(t)−ˆ
N(t)i(1)
where φ(k)is the set of transitions which fire at time
kand ˆ
O(t)and ˆ
N(t)indicate the columns of ˆ
Oand
ˆ
N, respectively, which correspond to the transition
t.
2.3 Boundedness, Reversibility and Liveness
The reachability set,R(G), of a TPN Gis the set of
all reachable states from the initial state. Although
it is rather complicated to describe the states, and
thus the reachability set, of a TPN (e.g., see, [18]),
the reachability set, R(ˆ
G), of the corresponding
SPN ˆ
G, can simply be described as the set of all
the markings ˆ
M, such that there exists a sequence
of enabled transitions which lead from the initial
marking ˆ
M0to ˆ
M. Furthermore, there is a one-to-
one correspondence between the states of ˆ
Gand of
G, thus, between R(ˆ
G)and R(G), [18].
For a bound vector K:P→N, a TPN Gis said
to be K-bounded if M(p)≤K(p),∀p∈P, for all
markings Mcorresponding to every state in R(G).
Gis said to be bounded if it is K-bounded for some
bounded K.Gis said to be reversible if for every
state S∈R(G), there exists a sequence of enabled
transitions which lead from Sto the initial state.
t∈Tis said to be live if for every state S∈R(G),
there exists a sequence of enabled transitions which
lead from Sto S0∈R(G)such that tis enabled at
S0. For T ⊂ T,Gis said to be T-live if every t∈ T
is live. Finally, Gis said to be live if it is T-live.
3 Supervisory Controller Design
In this section we consider supervisory controller
design to enforce boundedness, reversibility and
liveness in a system modeled by a TPN where both
transitions and places are timed. Since it is easier to
represent the state of the TPN using its SPN, we first
design a controller for the SPN and then describe
the corresponding controller for the original TPN
(OPN). Since there is a one-to-one correspondence
between the states of the SPN ˆ
Gand of the OPN G,
we have the following:
•Gis bounded if and only if ˆ
Gis bounded.
•Gis reversible if and only if ˆ
Gis reversible.
•Gis live if and only if ˆ
Gis live.
Thus, a controller which guarantees boundedness,
reversibility and liveness in the SPN also guarantees
boundedness, reversibility and liveness in the OPN.
Furthermore, such a controller also avoids deadlock,
since deadlock can not occur in a live Petri net, [20].
To design a controller for the SPN, first, for a
given bound vector ˆ
K:ˆ
P→N, we determine the
bounded reachability set,RB, of ˆ
G. The bounded
reachability set is the largest subset of R(ˆ
G)such
that any ˆ
M∈RBis bounded by ˆ
K(i.e., ˆ
M(p)≤
ˆ
K(p),∀p∈ˆ
P) and can be reached from ˆ
M0by
passing through only states which are bounded by
ˆ
K. Note that, although R(ˆ
G)may include infinitely
many elements for an unbounded Petri net, [15],
RBis always a finite set. Algorithm 1, which is
obtained by properly modifying Algorithm A in [19],
constructs the bounded reachability set, RB. The
function τ(m), used in Algorithm 1, returns the set
of sets of simultaneously enabled transitions at state
mand ρ(m, φ)returns the next state, as given by (1),
when φfires at m. Algorithm 1 returns an empty set
for RBif ˆ
M0(p)>ˆ
K(p), for some p∈ˆ
P. In such
a case, ˆ
Gis not ˆ
K-bounded at the initial time and,
hence, there exists no controller which can enforce
ˆ
K-boundedness.
Once the bounded reachability set, RB6=∅,
is constructed as above, we construct the bounded
reversible reachability set,RS. This set is the largest
subset of RBsuch that for any ˆ
M∈RSeither
ˆ
M=ˆ
M0or ˆ
Mcan be reached from ˆ
M0and ˆ
M0
can be reached from ˆ
Mwithout passing through
any markings outside RS. Algorithm 2, which is
obtained by properly modifying Algorithm B in
[19], constructs this set. Besides RS, this algorithm
also returns the set of all live transitions, ˆ
T. Here,
functions τand ρare as in Algorithm 1 and the
function (m)returns the set of enabled transitions
at state m.
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Algorithm 1 : Algorithm to construct RB
Inputs: ˆ
G= ( ˆ
P , ˆ
T , ˆ
N, ˆ
O, ˆ
M0)and ˆ
K
Output: RB
if ˆ
M0≤ˆ
Kthen
RB=R1={ˆ
M0}
loop
R2=∅
for i= 1 to |R1|do
m= [R1]i
Φ = τ(m)
for j= 1 to |Φ|do
φ= [Φ]j,ˆm=ρ(m, φ)
if ˆm /∈(R2∪RB)and ˆm≤ˆ
Kthen
R2←R2∪ { ˆm}
end if
end for
end for
if R2== ∅then
exit loop
end if
RB←RB∪R2
R1=R2
end loop
else
RB=∅
end if
return RB
Once the bounded reversible reachability set, RS,
is determined, a controller which keeps the state
of the SPN within RSguarantees ˆ
K-boundedness
and reversibility simultaneously for the SPN. Such
a controller can be described as
c(m, φ) := 1,if ρ(m, φ)∈RS
0,otherwise ,(2)
for any m∈RSand for any φ∈τ(m), where
c(m, φ) = 0 means that the firing of the set φat
state mis disabled by the controller and c(m, φ) =
1means that the firing of this set at state mis
not disabled by the controller. This controller also
guarantees liveness, if and only if ˆ
T=ˆ
T, where
ˆ
Tis as returned by Algorithm 2. Otherwise, ˆ
Tis
the largest subset of ˆ
Tsuch that a controller exists
which guarantees ˆ
K-boundedness, reversibility, and
ˆ
T-liveness simultaneously.
Algorithm 2 : Algorithm to determine RSand ˆ
T
Inputs: ˆ
G= ( ˆ
P , ˆ
T , ˆ
N, ˆ
O, ˆ
M0)and RB
Outputs: RSand ˆ
T
RX=RB,ˆ
T=∅
Start: R0=RX\ { ˆ
M0},RS={ˆ
M0}
loop
R=R0,F lag = 0
for i= 1 to |R|do
¯m= [R]i,Φ = τ( ¯m)
for k= 1 to |Φ|do
φ= [Φ]k,ˆm=ρ( ¯m, φ)
if ˆm∈RSthen
RS←RS∪ { ¯m},R0←R0\ { ¯m},
F lag = 1,go to Break
end if
end for
Break: continue
end for
if F lag == 0 then
exit loop
end if
end loop
if RS== {ˆ
M0}then
go to Finish
end if
RR=∅,Ra={ˆ
M0}
loop
Rb=∅,RR←RR∪Ra
for i= 1 to |Ra|do
¯m= [Ra]i,Φ = τ( ¯m)
for j= 1 to |Φ|do
φ= [Φ]j,ˆm=ρ( ¯m, φ)
if ˆm∈RSand ˆm /∈RR∪Rbthen
Rb←Rb∪ { ˆm}
end if
end for
end for
if Rb== ∅then
exit loop
end if
Ra=Rb
end loop
if RS6=RRthen
RX=RR,go to Start
end if
for i= 1 to |RS|do
¯m= [RS]i,T1=( ¯m)
for j= 1 to |T1|do
t= [T1]j
if ρ( ¯m, {t})∈RSthen
ˆ
T ← ˆ
T ∪ {t}
end if
end for
end for
Finish: return RS,ˆ
T
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4 Example
We borrow the automated manufacturing system
example presented in [13]. The TPN model of the
system is shown in Fig. 1. The corresponding SPN is
shown in Fig. 2. We aim to design a controller which
enforces ˆ
K-boundedness for ˆ
K(p) = 2,∀p∈ˆ
P,
reversibility, and liveness simultaneously. Algorithm
1 returns the bounded reachability set, RB, shown
in Table 1, where the ordering of the places is as
follows: p1,pp1
1,pt1
1,p2,pp2
1,pt2
1,pt2
2,p3. This set is
same as the reachability set R(ˆ
G), obtained in [13],
since the system is already ˆ
K-bounded. Algorithm
2 then determines that
RS={m0, m1, m2, m3, m7, m8, m9, m13, . . . , m24}
and ˆ
T=ˆ
T. Thus, the states m4,m5,m6,m10,
m11, and m12 are excluded from RS, since it is not
possible to reach to ˆ
M0=m0from any one of these
states. The controller described by (2) then disables
t1at states m1,m2, and m3and t2at states m7,m8,
and m9. Thus, a controller which disables firing t1
at states corresponding to m1,m2, and m3and t2at
states corresponding to m7,m8, and m9in the OPN
guarantees boundedness, reversibility and liveness in
the OPN. Furthermore, this controller also avoids
deadlock, since the controlled system is live.
5 Conclusions
Supervisory controller design to enforce bounded-
ness, reversibility, and liveness in DES modeled
by TPNs where both transitions and places are
timed has been considered. A controller design ap-
proach which uses the approach of stretching has
been proposed. The approach produces a supervi-
sory controller which guarantees boundedness and
reversibility simultaneously. The designed controller
also guarantees T-liveness for the largest possi-
ble subset Tof the set of transitions. Therefore,
boundedness, reversibility, and liveness are enforced
simultaneously whenever possible. Furthermore, the
designed controller is maximally permissive in the
sense that no transitions are disabled unnecessarily
and the reachability set of the controlled system is
the largest possible set in which boundedness and
reversibility can be enforced simultaneously.
The algorithms proposed for controller design
terminates in finite time. The computational com-
plexity of Algorithm 1 is proportional to the size
Table 1. Bounded reachability set, RB.
m0=02000000T
m1=01100000T
m2=01010000T
m3=01001000T
m4=00101000T
m5=00011000T
m6=00002000T
m7=01000100T
m8=01000010T
m9=01000001T
m10 =00000101T
m11 =00000011T
m12 =00000002T
m13 =00100100T
m14 =00010010T
m15 =00001001T
m16 =00010100T
m17 =00001010T
m18 =00001100T
m19 =00001010T
m20 =00100010T
m21 =00010001T
m22 =00001001T
m23 =00100001T
m24 =20000000T
of RB, which is related to both the size of the
Petri net and the bound vector. The computational
complexity of Algorithm 2, on the other hand, is
at worst proportional to the square of the size of
RB. Therefore, the overall computational complexity
of the proposed design approach is bounded by the
square of the size of RB.
The proposed controller design uses the so-called
behavioral approach, [20], [21], as opposed to the
so-called structural approach, [22], [23]. Although
behavioral approach is more tedious (as it requires
the construction of the reachability set), it can
guarantee the design of maximally permissive con-
trollers; whereas the structural approach, in general,
produces conservative controllers, [22].
As discussed in [24], to model some DES, it
may be necessary to use Petri net models in which
the arcs are timed. A Petri net in which arcs are
timed can be called a timed-arc Petri net (TAPN).
Therefore, as a future study, the present approach
can be extended to TAPNs. Furthermore, the present
approach can also be extended to decentralized su-
pervisory controller design along the lines of [25].
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Sources of Funding
This work has been supported by the Scientific
Research Projects Commission of Eskis¸ehir Techni-
cal University under grant numbers 22ADP301 and
23ADP033.
Conflicts of Interest
The author has no conflicts of interest to declare that
are relevant to the content of this article.
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(Attribution 4.0 International , CC BY 4.0)
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stages from the formulation of the problem to the
final findings and solution.
WSEAS TRANSACTIONS on SYSTEMS
DOI: 10.37394/23202.2023.22.75
Altug Iftar
E-ISSN: 2224-2678
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Volume 22, 2023
