and pipelining. The filter's throughput, energy efficiency, and latency, as well as the complexity of its

technology, all need to be improved. By adopting pipelining technique, the arithmetic processes of addition and

multiplication are separated. The break addition procedure is retimed. The architecture of Pipelining and

Retiming with m-tap filters and n-bit word lengths were designed. The smallest delay achieved by the proposed

distributed arithmetic-based FIR Filter with pipelining was 2.564ns for a 4tap implementation receiving an 8bit

input, while the largest delay achieved was 56.04ns for a 64-tap implementation receiving a 32-bit word length.

Delays as low as 0.68ns for a 4-tap implementation receiving an 8-bit input and as high as 4.53ns for a 64tap

implementation receiving a 32bit word length have been achieved by using the suggested distributed

arithmetic-based FIR Filter with retiming approach. Delay has been reduced by 73.2% for 4tap with 8bit input

and by 91.9% for 64tap with 32bit word length compared to the pipelining approach.

one of the principal blocks in DSP systems.

Multiplication processes, which result in the

excessive area, delay, and power consumption, are

the main issue with FIR filters, [4], [5]. Higher order

filters will be difficult to construct in real-time since

the number of multiply and accumulate operations

needed per filter rises linearly with filter order, [6].

The majority of applications in real-time digital

signal processing (DSP) systems need high

throughput and energy-efficient FIR filter designs.

with sequential circuits are covered by Jalaja et al.

direct form filters at the expense of more

sophisticated hardware. Carry increment adders

(CIA) and Vedic multipliers were used by Thakral

et al. [12], to apply an unfolding transformation to

an FIR filter. Wallace multiplier was used by Swati

and Himanshu, [13], to build the FIR filter.

According to [14] discusses two variations of

enhanced booth multipliers and efficient hybrid

adders.

For the implementation of the FIR filter, Rai et al.

difficult and may be implemented with retiming

technique. According to Meher and Park [17]

employed two-level pipelining to boost the

throughput of the FIR filter used in the adaptive

algorithm at the expense of a modest increase in

area and latency.

Meher [18] looked at several pipelining options for

DSP circuits. By pipelining to structural adders,

Mathias et al. [19], enhanced the CPD of transposed

form FIR filters at the price of more sophisticated

Multiplication (CMVM) instead of conventional

multiplication, where delay can be optimized by

using pipelining method. Using retiming and

redesigned CSLA-based adders, Pramod and

Shahana [23], created two types of high throughput

FIR filters.

The rest of this paper is structured as follows. The

Distributed Arithmetic Residue Number System is

explained in section 2. The proposed pipelining and

retiming methods were discussed in section 3. The

Table 1. DA-LUTs-based FIR Filter with the

The critical path, Logic Elements, and power

be divided into two portions by the two-level

pipelining. It should be mentioned that the retiming

won't cause delay. The pipelining delay distinguish

the multiplication and addition operations and limits

the critical path delay to .

Where  is the worst case combinational path

delay of the multiplication section and  is the

worst case combinational path delay of the addition

section.

Fig. 3: Retiming circuit of FIR Filter design

Here, the addition portion has been retimed to

decrease the worst-case addition latency. Here, the

FIR filters have been developed using this method.

The clock period and the number of registers needed

availability of the first output data in the pipelined

system and the sequential system. For example, if

latency is 1 clock cycle, then the kth output is

available in (k+1)th clock cycle in a 1-stage

pipelined system. As a result, each computation

takes 2 clock cycle to propagate through the system,

consumption must be as minimum as possible. The

filters.

Table 3. Performance analysis of FIR filter with a

A delay of 2.564ns was achieved for a 4tap, 8bit

input using the suggested distributed arithmetic-

based FIR Filter with pipelining approach, while a

produced by a 4 tap with 4 bit is 275.41MHz, and

for 64 taps with a 32bit word, the length is

17.53MHz.The maximum power consumed for

different taps with different bits is varied from

65.29mW to 73.50mW. The performance analysis

for 4 tap to 64 tap with 4 bit to 32 bit was compared

in Table 3.

Delays as low as 0.687ns for a 4tap implementation

receiving an 8-bit input and as high as 4.535ns for a

delay is reduced a lot but due to the addition of an

based computation. When compared with the

previous works in Table 5, pipelined DA RNS-

based FIR filter is decreased by 57.01% in the area

(LE's), decreased by delay by 22.55%, decreased by

66.69% in ADP, PDP was decreased by 22.39% and

increased by 19.47% in maximum frequency.

distributed arithmetic-based FIR filter, the resulting

used to test and validate their operation. To meet the

needs of the ALTERA CYCLONE III logic family

devices in 65nm technology, the RNS design

requirements, and FIR filter designs were generated

in the FPGA QUARTUS II 9.0 online version. This

paper compares various RNS FIR filters and the

design with retiming proves to be a better option

with improvement in performance in terms of delay.

For an 8-bit input and a 4-tap FIR filter, the

suggested distributed arithmetic-based FIR filter

suggested distributed arithmetic-based FIR filter

with retiming approach. Delay has been reduced by

73.2% for 4tap with 8-bit input and by 91.90% for

64-tap with 32-bit word length compared to the

pipelining approach.