4ca64232-6028-4c65-9d65-ff535972d41c20240402053929496wseas:wseasmdt@crossref.orgMDT DepositWSEAS TRANSACTIONS ON ELECTRONICS2415-15131109-944510.37394/232017http://wseas.org/wseas/cms.action?id=13363123202412320241510.37394/232017.2024.15https://wseas.com/journals/electronics/2024.phpRajath IthalH. L.Department of Electronics & Communication Engineering, R. V. College of Engineering, Bangalore, Affiliated to Visvesvaraya Technological University, Belagavi-590018, Karnataka, INDIAShylashreeN.Department of Electronics & Communication Engineering, R. V. College of Engineering, Bangalore, Affiliated to Visvesvaraya Technological University, Belagavi-590018, Karnataka, INDIAMamathaA. S.Department of Electronics & Communication Engineering, NITTE (Deemed to be University), NMAM Institute of Technology, Nitte-574110, Karnataka, INDIANikhilB. G.Signal Chip, Bangalore, Karnataka, INDIAConstant transconductance (Gm) biasing circuits, as the name suggests, generate a bias current that ensures that the Gm of a MOS transistor remains constant. The Gm of a MOS transistor is a very important parameter as various other parameters of a circuit such as the gain, UGB (Unity Gain Bandwidth, poles, and zeros are strongly dependent upon it. Every analog circuit in a chip is subjected to varying PVT (Process, Voltage, and Temperature) conditions. This leads to a varying Gm of the devices, and hence the parameters such as the gain and UGB also tend to vary. Hence, constant Gm biasing is crucial in systems, where the parameters are expected to be constant regardless of the external factors. The majority of constant Gm biasing circuits make use of an external off-chip resistor. While this is a reasonable solution, it adds to the cost, area, and complexity of the solution. Hence, it is vital to model and design all the required functionalities within the chip, eliminating the requirement for any external components. In this paper, different architectures of constant Gm biasing circuits are designed and simulated in Cadence Virtuoso software. The proposed architecture has an error of 6.42% in the variation of transconductance, which is a significant improvement concerning the other architectures simulated. Additionally, the proposed architecture does not require any off-chip components while the other architectures require an off-chip resistor. Hence, the proposed solution has reduced cost and complexity.42202442202417263https://wseas.com/journals/electronics/2024/a065117-004(2024).pdf10.37394/232017.2024.15.3https://wseas.com/journals/electronics/2024/a065117-004(2024).pdfB. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Education, 2000, ISBN: 978-0072380323. 10.1109/vlsid.2015.48I. Mondal and N. Krishnapura, “Accurate constant transconductance generation without off-chip components,” 28th International Conference on VLSI Design, 2015, pp. 249– 253. doi: 10.1109/VLSID.2015.48. 10.1109/101.55332J. Steininger, “Understanding wide-band MOS transistors,” IEEE Circuits and Devices Magazine, vol. 6, no. 3, 1990, pp. 26–31, doi: 10.1109/101.55332. 10.1109/asicon.2009.5351461Y. Chen and Y. Zhou, “A low power CMOS mixed-integrator-based continuous-time filter,” IEEE 8th International Conference on ASIC, 2009, pp. 274–276. doi: 10.1109/ASICON.2009.5351461. 10.1109/tcsii.2021.3049518S. Lee and E. S´anchez-Sinencio, “Current reference circuits: A tutorial,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 3, pp. 830–836, 2021. doi: 10.1109/TCSII.2021.3049518. 10.1109/ssmsd.2003.1190406J. Chen and B. Shi, “Novel constant transconductance references and the comparisons with the traditional approach,” Southwest Symposium on Mixed-Signal Design, pp. 104–107, 2003 doi: 10.1109/SSMSD.2003.1190406. 10.1109/tcsii.2016.2634779D. Osipov and S. Paul, “Temperaturecompensated β -multiplier current reference circuit,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp. 1162–1166, 2017. doi: 10.1109/TCSII.2016.2634779. 10.1109/iscas.2004.1328281S. Pavan, “A fixed transconductance bias technique for CMOS analog integrated circuits” IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 1– 661, 2004, doi: 10.1109/ISCAS.2004.1328281. 10.1109/pacet.2017.8259966N. Baxevanakis, I. Georgakopoulos, and P. P. Sotiriadis, “Rail-to-Rail operational amplifier with stabilized frequency response and constant-gm input stage,” Panhellenic Conference on Electronics and Telecommunications, pp. 1–4, 2007 doi: 10.1109/PACET.2017.8259966. 10.1109/cas50358.2020.9267977A. C. Veselu, C. Stanescu, and G. Brezeanu, “Low current constant gm technique for railto-rail operational amplifiers,” International Semiconductor Conference, pp. 253–256, 2020, doi: 10.1109/CAS50358.2020.9267977. 10.1109/tcsii.2022.3158358S. Pavan, “Systematic development of CMOS fixed-transconductance bias circuits,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 5, pp. 2394–2397, 2022. doi: 10.1109/TCSII.2022.3158358. 10.1109/tcsi.2022.3188707M. Lee and K. Moez, “A 0.5–1.7 v efficient and pvt-invariant constant subthreshold gm reference circuit in CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 10, pp. 3915– 3926, 2022. doi: 10.1109/TCSI.2022.3188707. 10.1109/iscas.2017.8050291U. A. Antao, J. C. M. Hsieh, and T. W. Berger, “A 9-nw on-chip constant subthreshold CMOS transconductance bias with fine-tuning,” IEEE International Symposium on Circuits and Systems, pp. 1–4, 2017, doi: 10.1109/ISCAS.2017.8050291. 10.37394/23201.2021.20.6Ghanshyam Singh, Hameed pasha, H. C. Hadimani, Shafiqul Abidin, Zuleka Tabbusm, "CMOS Realization of Fully Electronically Tunable Single Resistance Control Mixed Mode Biquad Filter Employing Single VDTA at +- 0.6V", WSEAS Transactions on Circuits and Systems, vol. 20, pp. 48-56, 2021, https://doi.org/10.37394/23201.2021.20.6. 10.1109/tcsii.2014.2345296C.Y. Chu and Y.J. Wang, “A pvt-independent constant- Gm bias technique based on analog computation,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 10, pp. 768–772, 2014. doi: 10.1109/TCSII.2014.2345296. 10.37394/23201.2020.19.34Hicham Akhamal, Mostafa Chakir, Hatim Ameziane, Mohammed Akhamal, Kamal Zared, Hassan Qjidaa, “A 916 nW Power LDO Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications”, WSEAS Transactions on Circuits and Systems, vol. 19, pp. 311-319, 2020, https://doi.org/10.37394/23201.2020.19.34.