This review paper explores various memory fault models
and their associated detection algorithms. Memory faults pose
significant challenges in the reliable operation of electronic
systems, and understanding their characteristics and detection
techniques is crucial for ensuring system robustness.
Let's analyse an example summary table that demonstrates
how various memory sizes are checked using various memory
methods, along with their time complexity. The patterns are
used at a rate of 100M read or write operations per second for
the computations in the table below.
Table 1: Example Summary Table.
Memo
ry Size
Time
Complexi
ty
(n)
Time
Complexi
ty
(n log n)
Time
Complexi
ty
(n^1.5)
Time
Complexi
ty
(n^2)
1 Kilo
Byte
0.0001
seconds
0.001
seconds
0.0033
seconds
0.105
seconds
1
Mega
Byte
0.102
seconds
2.04
seconds
1.83
minutes
1.27
days
1 Giga
Byte
1.75
minutes
52.48
minutes
40.8
days
3659
years
We can infer from the above Table 1 how lengthy memory
testing might be if an appropriate test algorithm is not
employed. Any algorithm that spans a number of days or years
is not linear in time. Such algorithms are intolerable and are
not supported by the semiconductor industry.
The paper investigates several memory fault models,
including stuck-at faults, transition faults, coupling faults, and
address decoder faults [5] [6]. To address these memory faults
[2], the paper discusses various detection algorithms
commonly employed in practice. Stuck-at faults occur when a
specific bit in memory remains constantly stuck at either 0 or
1. Transition faults involve errors during state transitions,
leading to incorrect data propagation. Coupling faults arise
from interactions between adjacent memory cells, potentially
causing data corruption. Address decoder faults pertain to
issues in memory address decoding, resulting in incorrect
memory access. The zero-one algorithm, known for its
simplicity, aims to detect stuck-at faults by ensuring that both
0 and 1 values are observed during memory read operations.
The checkerboard algorithm verifies memory integrity by
writing alternating 0’s and 1’s and then reading back to
identify any inconsistencies. March algorithms, a family of
sophisticated test algorithms, systematically march through
memory locations, stimulating specific patterns and detecting
faults based on observed responses [8].
By thoroughly reviewing these memory fault models and
detection algorithms, this paper provides valuable insights
into the challenges associated with ensuring memory
reliability in electronic systems. The findings contribute to the
A Review Paper on Memory Fault Models and its Algorithms
KENDAGANNA SWAMY S.1, RAJASREE P. M.1, ANAND M SHARMA1,
JNANAPRAKASH J NAIK2
1Dept. of Electronics and Instrumentation R V College of Engineering Bengaluru, INDIA
2Dept. of Electronics and Communictation R V College of Engineering Bengaluru, INDIA
Abstract: —The significance of testing semiconductor memories has grown significantly in the semiconductor
industry due to the increased density of modern memory chips. This paper aims to investigate and analyze
different types of functional faults present in today's memory technology. These faults include stuck-at faults,
transition faults, coupling faults, address decoder faults, and neighborhood pattern-sensitive faults. The paper
also delves into the techniques utilized to identify and detect these faults. In particular, the focus is placed on
the importance of zero-one, checkerboard, and March pattern tests, which are widely employed to assess
functional memory defects at different levels, such as the chip level, array level, and board level. Furthermore,
the study provides an in-depth exploration of various test algorithms and thoroughly examines their fault
coverage capabilities. Overall, this review paper provides valuable insights into the challenges posed by the
dense nature of modern memory chips and offers a comprehensive analysis of functional faults in memory
technology. By emphasizing the importance of testing and presenting a detailed exploration of fault detection
methods and test algorithms, this study contributes to the advancement of reliable and high-performance
memory devices in the electronic industry suggesting that MARCH algorithms outperform others when
considering factors like fault coverage, power efficiency, area optimization, and time complexity parameters,
making them the preferable choice for reliable and high-performance memory devices in the electronic industry.
Key-words:— Memory Faults, Memory Test Algorithms, BIST (Built in Self-Test), Memory array, March test,
MATS, Up Transition, Down Transition, MSCAN, DFT, Fault coverage
Received: October 9, 2023. Revised: August 18, 2024. Accepted: September 9, 2024. Published: October 7, 2024.
1. Introduction
International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
Kendaganna Swamy S., Rajasree P. M.,
Anand M. Sharma, Jnanaprakash J. Naik
143
Volume 6, 2024
advancement of fault-tolerant designs and enhance the overall
dependability of memory subsystems
A stuck-at fault (SAF) arises when a cell or line
consistently holds a value of either 0 (known as a stuck-at-0
fault as shown in Figure 1) or 1 (known as a stuck-at-1 fault
as shown in Figure 2). An effective test for identifying all
SAFs ensures that both 0 and 1 can be observed when reading
from each cell [20].
Figure 1: State diagram for s-a-0 memory cell.
Figure 2: State diagram for s-a-1 memory cell.
Transition faults (TFs) are specific faults that can occur in
digital circuits when a cell or logic element fails to transition
from one state to another during a write operation. In normal
operation, signals transition between the 0 and 1 states
representing low and high voltage levels. However, transition
faults can result in cells getting stuck in a particular state,
either 0 or 1, when they were supposed to transition.
There are two types of transition faults: up-transition faults
and down-transition faults.
i) In Figure 3 an up-transition fault (<
↑
| 0 >) occurs
when a cell fails to transition from 0 to 1 as expected,
resulting in the output remaining stuck at 0.
Figure 3: State diagram for up transition faults.
j) In Figure 4 an down-transition fault (<
↓
| 1>)
happens when a cell fails to transition from 1 to 0, causing
the output to remain stuck at 1.
Figure 4: State diagram for down transition faults.
These faults can affect the decoding circuitry, which
interprets memory addresses and chooses the proper memory
cell for read or write operations, in memory systems.
Decoding the memory address bus and producing control
signals to choose the proper memory cell for the desired
operation are tasks carried out by the address decoder. The
address decoder of a memory is made up of a row and column
decoder. Four sorts of defects in the address decoder are taken
into consideration from the perspective of memory testing.
AF1: It is impossible to access any word with a specific
address.
AF2: There is no address that allows access to a specific
word.
AF3: Multiple words can be accessed at the same time
using certain addresses.
AF4: One particular word can be accessed through
multiple addresses.
Coupling faults (CFs) are a type of fault that occurs in a
cell within a digital circuit due to its coupling or interaction
with other cells. These faults arise when the behaviour of a
cell is affected by the neighbouring cells, leading to irregular
or erroneous operation.
In the context of coupling faults, there can be an
exponential number of combinations in which a cell can be
coupled with other cells in a circuit. Each coupling
combination can result in unique fault behaviour, making it
challenging to identify and diagnose these faults. The widely
used coupling fault model assumes that any two cells in the
circuit can be coupled together, resulting in abnormal
behaviour or faulty operation within those two cells. This
model is known as the 2-cell coupling fault model, as it
focuses on the interaction between pairs of cells.
Considering a memory with n cells, the number of 2-cell
coupling faults can be determined using the combination
formula nC2, also known as "n choose 2". This formula
calculates the number of ways to choose 2 cells out of a total
of n cells for coupling analysis. The result represents the
number of unique coupling combinations and, consequently,
the potential number of 2-cell coupling faults present in the
circuit. This is represented in Figure 5.
Figure 5: Write operation state diagram between two good
memory cells.
2. Memory Fault Models
2.1 Stuck at Fault (SAFs)
2.2 Transition Fault (TF)
2.3 Address Decoder Faults (ADFs)
2.4 Coupling Faults (CFs)
International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
Kendaganna Swamy S., Rajasree P. M.,
Anand M. Sharma, Jnanaprakash J. Naik
144
Volume 6, 2024
i. Inversion Coupling Faults (CFin):
Inversion Coupling Faults (CFin) are a specific type of
coupling fault that occurs in digital memory cells. These
faults involve an upper (0 to 1) or lower (1 to 0) transition
write operation in an aggressor word, which leads to an
inversion in the cell of a victim word.
In the context of CFin, the aggressor word refers to the
word or cell that triggers the coupling effect, while the victim
word is the word or cell that experiences the inversion due to
the coupling. When an aggressor word undergoes a write
operation with a transition from 0 to 1 (rising) or from 1 to 0
(falling), it causes an inversion in the content of the victim
cell.
The two types of CFin are rising and falling inversions,
each corresponding to a specific transition in the aggressor
word.
As represented in Figure 6, the rising inversion is
represented as < ↑ | ↕ >, indicating that a change from 0 to 1
in the aggressor cell complements or inverts the content of
the victim cell.
Figure 6: State diagrams of rising inversion coupling
faults.
As represented in Figure 7, the falling inversion is
represented as < ↓ | ↕ >, indicating that a change from 1 to 0
in the aggressor cell complements the content of the victim
cell.
Figure 7: State diagrams of falling inversion coupling
faults.
It is important to note that inversion coupling faults are
not typically observed in faulty memory cells and are defined
mainly for historical reasons. Therefore, they are not included
in the linked faults list, which refers to the list of faults
identified as actual observable faults in a memory system.
ii. Idempotent Coupling Faults (CFid):
Idempotent coupling faults (CFid) are a specific type of
coupling fault that occurs when a write operation on an
aggressor word cell forces a certain value (0 or 1) in a victim
word cell. These faults are a subset of coupling faults (CFs)
and are characterized by the fact that the write operation
causes a flip in the content of the victim cell from its previous
state.
There are four variations of idempotent coupling faults:
1) Rising 0: In this scenario, denoted as < ↑ | 0 >, a 0 to
1 transition in an aggressor word cell leads to the content of
the victim cell being set to 0.This is represented in Figure 8.
Figure 8: State diagrams of rising 0 idempotent coupling
faults.
2) Rising 1: Represented as < ↑ | 1 >, this fault occurs
when a 0 to 1 transition in an aggressor word cell results in
the content of the victim cell being set to 1.This is represented
in Figure 9.
Figure 9: State diagrams of rising 1 idempotent coupling
faults.
3) Falling 0: This fault is indicated by < ↓ | 0 > and
occurs when a 1 to 0 transition in an aggressor word cell
causes the content of the victim cell to be set to 0. This is
represented in Figure 10.
International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
Kendaganna Swamy S., Rajasree P. M.,
Anand M. Sharma, Jnanaprakash J. Naik
145
Volume 6, 2024
Figure 10: State diagrams of falling 0 idempotent coupling
faults.
4) Falling 1: Denoted as < ↓ | 1 >, this fault happens
when a 1 to 0 transition in an aggressor word cell sets the
content of the victim cell to 1. This is represented in Figure
11.
Figure 11: State diagrams of falling 1 idempotent coupling
faults.
In each of these fault scenarios, the write operation on the
aggressor cell induces a specific value in the victim cell,
overriding its previous content. These idempotent coupling
faults can lead to erroneous behavior and data corruption
within the circuit.
Identifying and addressing idempotent coupling faults is
essential for ensuring the integrity and reliability of digital
systems. Techniques such as fault simulation, testing, and
analysis are employed to detect and mitigate these faults
during the design, manufacturing, or maintenance stages of
the circuit, helping to enhance overall system performance
and dependability.
iii. Static Coupling Faults (CFst):
Static coupling faults (CFst) refer to a specific type of
coupling fault that occurs when a given value (0 or 1) in a
cell, known as the aggressor word, influences or forces a
specific value (0 or 1) in a cell of another word, known as the
victim word. These faults occur due to the coupling or
interaction between the aggressor and victim cells.
There are four possible scenarios that describe static coupling
faults:
1) (0 in cell A sets the content of the cell V to be 0): In this
scenario, when the value of cell a in the aggressor word is 0,
it influences the cell v in the victim word to also have a value
of 0. The coupling between these cells causes the content of
cell v to be forced to 0. This is represented in Figure 12.
Figure 12: 0 in cell A sets the content of the cell V to be 0.
2) (0 in cell A sets the content of the cell V to be 1): Here,
if cell a in the aggressor word has a value of 0, it causes the
content of cell v in the victim word to be forced to 1. The
coupling between the cells leads to an undesired change in
the content of cell v. This is represented in Figure 13.
Figure 13: 0 in cell A sets the content of the cell V to be 1.
3) (1 in cell A sets the content of the cell V to be 0): This
scenario occurs when cell a in the aggressor word has a value
of 1, resulting in the content of cell v in the victim word being
forced to 0. The coupling between these cells causes an
unexpected change in the content of cell v. This is represented
in Figure 14.
Figure 14: 1 in cell A sets the content of the cell V to be 0.
4) (1 in cell A sets the content of the cell V to be 1): In this
case, when the value of cell a in the aggressor word is 1, it
forces the content of cell v in the victim word to be 1. The
International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
Kendaganna Swamy S., Rajasree P. M.,
Anand M. Sharma, Jnanaprakash J. Naik
146
Volume 6, 2024
coupling between these cells leads to a change in the content
of cell V as shown in Figure 15.
Figure 15: 1 in cell A sets the content of the cell V to be 1.
Neighbourhood pattern sensitive coupling faults represent
a distinct category of faults that emerge from the interplay
between a cell under examination and the arrangement of
neighbouring cells within a digital circuit. In this type of fault,
the behaviour of the affected cell, known as the victim cell,
undergoes an influence or alteration based on the values or
states exhibited by the neighbouring cells. The neighbourhood
of a cell refers to the collection of cells in close proximity or
directly connected to the cell being tested. These neighbouring
cells possess the potential to exert a significant impact on the
performance and functionality of the victim cell.
When a neighbourhood pattern sensitive coupling fault
arises, the coupling effect between the cell under scrutiny and
its neighbouring cells leads to the victim cell exhibiting
incorrect behaviour [7]. The specific pattern formed by the
neighbouring cells' values or states introduces a disturbance
that interferes with the operation of the victim cell, resulting
in erroneous outputs or impaired functioning.
The coupling effect can manifest in various forms,
including the introduction of electrical noise, signal
interference, or unintended propagation of signals between
cells. In Figure 16, the particular coupling pattern formed by
the neighbouring cells serves as the determining factor for the
nature of the faulty behaviour exhibited by the victim cell.
Type-1 Neighbourhood Faults: The blue coloured cell is
known as base cell. The base cell is the cell which undergoes
testing when the four cells around it is in the coupling state.
The four cells (pink colour blocks) are neighbourhood cells
for the base cell. This fault pattern is shown in Figure 16 and
example of this is describes in Figure 17.
Figure 16: Pattern of Type-1 Neighbourhood Faults.
Figure 17: Example of Type-1 Neighbourhood Faults.
Type-2 Neighbourhood Faults: It has eight
neighbourhood cells corresponding around the cell under test.
These faults result in more complex when compared to type-
1 neighbourhood. This fault pattern is shown in Figure 18 and
example of this is describes in Figure19.
Figure 18: Pattern of Type-2 Neighbourhood Faults
1
4
0
2
3
Cell
Cell
Cell under
coupling
Cell under
test
Cell under
test
Cell under
coupling
Cell
Cell under
test
Cell under
coupling
2.5 Neighbourhood Pattern Sensitive Coupling Faults
International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
Kendaganna Swamy S., Rajasree P. M.,
Anand M. Sharma, Jnanaprakash J. Naik
147
Volume 6, 2024
Figure 19: Example of Type-2 Neighbourhood Faults
MSCAN Algorithm is also known as the zero-one
algorithm. This algorithm has four major steps:
• Write zero to every cell.
• Read zero from every cell.
• Write one to every cell.
• Read one from every cell.
This Algorithm detects all stuck at faults (SAF) and rising
transition faults but fails to detect falling transition faults [8].
It also fails to detect all Address decoder faults and Coupling
faults. The complexity of the circuit is 4N as 4 operations takes
place in each cell [3] [19].
Checkerboard is a commonly used algorithm in memory
Built-In Self-Test (BIST) for detecting and locating faults in
memory arrays. It is based on the principle of alternating
memory patterns to detect faults in the memory array [22]. The
checkerboard algorithm works by writing a specific pattern of
alternating 1s and 0s to the memory array. The pattern is
written in a way that creates a checkerboard-like pattern of
alternating 1s and 0s. Once the pattern is written, the algorithm
reads back the data and checks for any errors or faults in the
memory array [10].
The time complexity of the checkerboard algorithm is the
same as a zero-one algorithm that is 4N. The checkerboard
algorithm is mainly used for detecting faults which are
resulting from leakage, shorts between cells, and data
retention faults [9]. The checkerboard pattern also detects
SAFs – Stuck at faults and half of the number of TFs –
Transition faults.
This Algorithm has 4 major steps
•Write checkerboard with up addressing order.
•Read checkerboard with up addressing order.
•Write inverse checkerboard with up addressing order.
•Read inverse checkerboard with up addressing order
March Algorithms are used to detect single bit error. Faults
can be manifested as errors. In this algorithm it performs two
operations [15] [16]. One is read and other is write operation.
The main aim is to read and write the address with a finite
sequence. It comprises a sequence of March elements in its
test pattern. This algorithm is greatly used in testing of
memories. There are some March notations like:
: It indicates the accessing of memory location from
lower address to higher address.
: It indicates the accessing of memory location from
higher address to lower address.
⇕: It is used to access user defined memory locations in
both directional.
r0: It performs read 0 operation in the cell.
r1: It performs read 1 operation in the cell.
w0: It performs write 0 operation in the cell.
W1: It performs write 1 operation in the cell.
This Algorithm has 4 major steps:
Increasing Address
• write 0s with up addressing order (to initialize)
• Read 0s, write 1s with up addressing order
• Read 1s, write 0s with up addressing order
Decreasing address
• Read 0s, write 1s with down addressing order
• Read 1s, write 0s with down addressing order
• Read 0s with down addressing order
i. MATS
MATS, which stands for Modified Algorithmic Test
Sequence, is a compact MARCH test used for unlinked
SAFs (Stuck-At Faults) in memory cell arrays and
read/write logic circuits. By treating the collective reading
of multiple cells as an OR function of their contents, this
algorithm is capable of detecting all faults in OR-type
technology[12] [16]. Moreover, the MATS Algorithm can
also be applied to AND-type technology by utilizing the
MATS-AND test sequence provided below [2]. With a
complexity of 4N, the MATS Algorithm offers superior
fault coverage compared to equivalent zero-one and
checkerboard tests.
𝑀𝐴𝑇𝑆 − 𝑂𝑅𝑡𝑦𝑝𝑒:
{
⇕ (𝑤0); ⇕ (𝑟0, 𝑤1); ⇕ (𝑟1)
}
𝑀𝐴𝑇𝑆 − 𝐴𝑁𝐷𝑡𝑦𝑝𝑒:
{
⇕ (𝑤1); ⇕ (𝑟1, 𝑤0); ⇕ (𝑟0)
}
ii. MATS+
The MATS+ test sequence detects all SAF’s and AF’s, its
often used instead of MATS when the technology used
0
1
2
3
4
5
6
7
8
Cell
Cell under
test
Cell under
coupling
3. Memory Fault Detection Algorithms
3.1 MSCAN Algorithm
3.2 Chekerboard Algorithm
3.3 Marching Algorithm
International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
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148
Volume 6, 2024
under test is unknown. The MATS+ algorithm has a test
complexity of 5N.
𝑀𝐴𝑇𝑆+:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1); ⇓ (𝑟1, 𝑤0)
}
iii. MATS++
It is any extension of MATS+ algorithm. It can detect
faults like AF, SAF and TF. In this algorithm the process
is complete with no repetition. It has complexity of 6N.
𝑀𝐴𝑇𝑆 + +:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1); ⇓ (𝑟1, 𝑤0, 𝑟0)
}
iv. MARCH X
It can detect faults like SAF, TF, AF and some CF. It has
complexity of 6N. There is no repetition in this algorithm.
It has simple test sequence to detect four faults. This is
represented in Table 2.
𝑀𝐴𝑅𝐶𝐻 𝑋:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1); ⇓ (𝑟1, 𝑤0); ⇕ (𝑟0)
}
Table 2 Fault coverage of different fault simulation algorithms for
various fault models.
v. MARCH Y
It is similar to March X algorithm. So, the complexity is
increased to 8N. It can detect faults like SAF, TF, AF and
some CF.
𝑀𝐴𝑅𝐶𝐻 𝑌:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1, 𝑟1); ⇓ (𝑟1, 𝑤0, 𝑟0); ⇕ (𝑟0)
}
vi. MARCH A
It has complexity of 15N. Here four elements as group in
each term. It can detect faults like SAF, TF, AF and some
CF. It is irredundant algorithm.
𝑀𝐴𝑅𝐶𝐻𝐴:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1, 𝑤0, 𝑤1); ⇑ (𝑟1, 𝑤0, 𝑤1);
⇓ (𝑟1, 𝑤0, 𝑤1, 𝑤0); ⇓ (𝑟0, 𝑤1, 𝑤0)
}
vii. MARCH B
It is similar to March A algorithm. So, the complexity is
increased to 17N. It can detect faults like SAF, TF, AF and
CF.
𝑀𝐴𝑅𝐶𝐻𝐵:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1, 𝑟1, 𝑤0, 𝑟0, 𝑤1); ⇑ (𝑟1, 𝑤0, 𝑤1);
⇓ (𝑟1, 𝑤0, 𝑤1, 𝑤0); ⇓ (𝑟0, 𝑤1, 𝑤0)
}
viii. MARCH C
It has complexity of 15N. It can detect faults like SAF, TF,
AF and CF. Here there is a repetition process so
complexity is more.
𝑀𝐴𝑅𝐶𝐻 𝐶:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1); ⇑ (𝑟1, 𝑤0);
⇕ (𝑟0); ⇓ (𝑟0, 𝑤1); ⇓ (𝑟1, 𝑤0); ⇕ (𝑟0)
}
ix. MARCH C-
It is the extension of March C algorithm. It has complexity
of 10N. It can detect faults like SAF, TF, AF and CF. Here
no repetition occurs.
𝑀𝐴𝑅𝐶𝐻 𝐶−:
{
⇕ (𝑤0); ⇑ (𝑟0, 𝑤1); ⇑ (𝑟1, 𝑤0);
⇓ (𝑟0, 𝑤1); ⇓ (𝑟1, 𝑤0); ⇕ (𝑟0)
}
Analysis of algorithms and their fault coverage
concerning Time complexity, Power dissipation for a 4
KB memory [25], and Area overhead in terms of gate
count for a 4 KB system. This is represented in Table 3.
ALG
Stuck
at
Fault
Transition
Fault
Address
Decoder
Fault
Coupling
Fault
Neighbor
hood
Pattern
Sensitive
Fault
MSCAN
Yes
Rising (<
↑ | 0 >)
No
No
No
Checkerb
oard
Yes
Half
(either < ↑
| 0 >
or
< ↓ | 1 >)
No
No
No
MATS
Yes
No
Yes
No
No
MATS+
Yes
Yes
Yes
No
No
MATS++
Yes
Yes
Yes
No
No
March X
Yes
Yes
Yes
Yes
No
March Y
Yes
Yes
Yes
Yes
No
March A
Yes
Yes
Yes
Yes
No
March B
Yes
Yes
Yes
Yes
No
March C
Yes
Yes
Yes
Yes
No
March C-
Yes
Yes
Yes
Yes
No
International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
Kendaganna Swamy S., Rajasree P. M.,
Anand M. Sharma, Jnanaprakash J. Naik
149
Volume 6, 2024
Table 3 Comparison of Power, Area and Timing.
Algorithms
Time
Complexity
Fault
Coverage
Power
Dissipation
(mW)
Area
Overhead
MSCAN
4N
Limited
70 - 80
280 - 300
Checker
board
4N
Limited
80 - 90
300 -340
MATS
4N
High
80 - 90
360 - 380
MATS+
5N
High
90 -100
400 - 430
MATS++
6N
High
100 -120
420 - 450
March X
6N
High
720 - 740
480 - 500
March Y
8N
High
750 - 765
510 - 530
March A
15N
High
690 -710
620 - 640
March B
17N
Very High
745 - 765
640 - 660
March C
15N
Very High
700 - 720
580 - 600
March C-
10N
Very High
680 - 700
560 -580
The ‘N’ denotes the time taken for each read and write
operation in the memory.
This review paper talks about how SRAM and DRAM
technologies mostly use functional testing with tests like zero-
one, checkerboard, and March patterns. These tests try to find
different types of faults, such as stuck-at faults or
neighbourhood pattern-sensitive faults. From this analysis, it's
apparent that the MSCAN algorithm consumes fewer gates,
resulting in lower power dissipation. However, it exhibits very
poor fault coverage. Conversely, March C- boasts the highest
fault coverage but entails increased power dissipation and area
overhead. Balancing these factors necessitates sacrificing one
parameter for better performance. Compared to traditional
methods like MSCAN and Checkerboard, the MATS,
MATS+, MarchX, MarchA, MarchY, and MarchB algorithms
showcase superior efficiency and fault coverage [18]. Despite
ongoing enhancements aimed at bolstering fault coverage in
existing algorithms, there remains a critical need for a novel
algorithm capable of efficiently detecting a wide array of fault
types [22]. As semiconductor memory density escalates,
research persistently pursues advanced pattern sequences and
alternative strategies such as DFT and BIST to fortify testing
capabilities. These efforts are aimed at meeting the evolving
challenges posed by advancing semiconductor technologies.
Emerging alternatives like MATP, GALPAT, Butterfly, and
Signature Analysis using LFSR promise enhanced results,
although the trade-off between parameters remains an
inevitable consideration.
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International Journal of Electrical Engineering and Computer Science
DOI: 10.37394/232027.2024.6.17
Kendaganna Swamy S., Rajasree P. M.,
Anand M. Sharma, Jnanaprakash J. Naik
151
Volume 6, 2024