FPGA Implementation of Enhanced Throughput Design of AES

Architecture using Nikhilam Sutra

BINDU SWETHA PASULURI, V. J. K. KISHOR SONTI

School of Electronics & Electrical Engineering

Sathyabama Institute of Science & Technology, Chennai- 600119,

INDIA

Abstract: The exponential growth of the internet and contemporary communications users have established

maximize speed. Parallelization of a key expansion module's sub-processes would be used to reduce the critical

chain latency. The S-box comprising sub-byte & inverse sub-byte operations has been developed with

compound field arithmetic operations to reduce time and area further. The work Increased throughput by 50%,

area reduced by 34.32 %, and latency by 20% compared to the old approach with modified nikhilam sutra.

Additionally, integrated AES encryption/decryption is planned and implemented on the FPGA Zed board

utilizing Verilog HDL in Xilinx Vivado.

Key-words: - Advanced encryption standard, throughput, FPGA, high security, nikhilam sutra

Received: September 17, 2021. Revised: August 18, 2022. Accepted: September 21, 2022. Published: October 31, 2022.

of the security components used to safeguard data

accessible to the public. Cryptography is a technique

of communication security in which data

representations are transformed from one

configuration to the other to cover up and safeguard

Cryptography's value continues to expand in

lockstep well with the volume of sensitive data

exchanged across open networks. The more data

delivered in a format understandable by a personal

Standard (AES) computations. The goal was to

AES has 3 different round procedures. A specific

input block, typically 128 bits in size, is required, as

is a comparable yield of the same size. The

conversion process necessitates adding a second

kind of information, which is the key. The cypher

determines the key length, and AES supports three

alternative key sizes: 128, 192, and 256 bits. Each of

the three primary sizes has been determined to be

acceptable for Federal Government various

function multiplies the value of the input key to

create a round key per round. The AES method is

based on a single 4x4 byte cluster known as a state.

The status changes four times during encryption:

Add Round Key, Substitution Byte (sub-byte), Shift

Row, and MixColumn (a combination of these four

Table 1. In AES, the width of the round key and the

number of iterations

Operations are referred to as a round); and for

decryption, the state undergoes four changes: Add

Round Key, converse sub-byte, transposed Shift

rows, and Inverse Mix column. The AddRoundKey

technique combines a bitwise XOR operation upon

that current state and the Key Expansion Function’s

Round Key. Encryption or decryption may be

performed in our integrated architecture by

crucial for reducing the AES architecture's area and

power consumption. The ROM-based method

consumes a huge memory space and introduces

substantial latency due to ROM access time. As a

consequence, composite field arithmetic facilitates

S-box completion. Cryptography's practical usage

for encryption is contingent upon properly

managing cryptographic keys. Greater is considered

to be superior. Because they can, and because it is

available, top-secret military applications may

The reverse multiplicative approach is obtained by

decomposing the much more complicated GF (28)

into the lower order fields GF (21), GF (22), and GF

((22)2). This would be done by the use of the

irreducible polynomials listed below:

GF (22) →GF (2): x2+x+1

GF ((22)2)) →GF (22): x2+x+φ (2,1)

GF (((22)2)2) →GF ((22)2): x2+x+λ

The multiplicative inverse formula could be

represented mathematically as an eight-by-eight

matrix. Let q become the vector from GF (28) and

explain the isomorphic and inverse relations. As δ*q

and δ-1*q.

Fig. 8: Completion of multiplication in GF in a

logical manner (2).

Multiplication with constant 𝝋

Assume k=q 𝜑, q and 𝜑={10} are components

in GF(22).

k= (q1x+q0)(10) =q1x2+q0x

By replacing x2=x+1, we can get k1=q1⊕q0,

k0=q0that can be logically implemented as

[5] can be performed as follows:

q3-1 =q3 ⊕q3q2q1 ⊕q3q0 ⊕q2

Within Mix Columns and Inverse Mix Columns

transformations, every column byte becomes

transformed to the correct value, a function among

all four bytes across the column. Every

transformation involves multiplying every byte of

the output shifting rows or reverse shift rows by a

predetermined matrix, which would then be sorted

as a state, [19].

good solution for digital electronics [12], [13]. This

paper provides an overview and application of the

notion of high-speed multiplier designs. The

multiplier concept has been extensively researched

in the Nikhilam and U T sutras.

Nikhilam Sutra

Furthermore, Nikhilam Sutra signifies 'all nine and

the final ten.' Even though it is valid across all

multiplication situations when the numbers are the

(96 * 93), we will first explain this Sutra, in which

the selected base is 100, which would be more

robust and more extensive than the two. Figure 13

depicts the Nikhilam sutra.

For a ‘00112233445566778899aabbccddeeff’

(128-bit in hexadecimal) and 256-bit key’

000102030405060708090a0b0c0d0e0f10111213

141516 1718191a1b1c1d1e1f’, enc- dec as 1,rst as 0

and clock inputs the encrypted data of 128-bit

‘ea2b7ca516745bfeafc49904b496089’ is generated.

By selecting the multiplexer selector as 1, the

encrypted data ‘ea2b7ca516749bf eafc 499

04b496089’ with256-bitkey

000102030405060708090a0b0c0d0e0f10111213

IEEE transactions on very large-scale

integration (VLSI) systems, Vol.12, No.9,

2004.

[6] Naga M. Kosaraju University of South

Florida, MuraliVaranasi, Saraju P. Mohanty,

University of North Texas, Denton TX 76203,

A High-Performance VLSI Architecture for

Advanced Encryption Standard (AES)

Algorithm.

Architectures for the AES Algorithm, IEEE

transactions on very large-scale integration

(VLSI) systems, Vol.12, No.9, 2004.

[9] Purnima Gehlot, S. R. Biradar, and B. P.

Singh MITS University, Implementation of

modified Two fish Algorithm using 128 and

192-bit keys on VHDL, International Journal

of Computer Applications, Vol.70, No.13,

2013.

Research (IJSR), Vol.5, No.12, 2016, pp. 239-

242.