Converters with Reduced Duty Cycle Range and Ground Connected to
the Positive Input Voltage Terminal
FELIX A. HIMMELSTOSS
Faculty of Electronic Engineering and Entrepreneurship,
University of Applied Sciences Technikum Wien,
Hoechstaedtplatz 6, 1200 Vienna,
AUSTRIA
Abstract: - A family of converters with reduced duty cycle range is treated here. Two-step-down, two step-up,
and four step-up-down converters are investigated. Four different voltage transformation ratios can be found.
For all converters, the large signal and the small signal models of the ideal case are given. Furthermore, the
connections of the operating point values and the voltage stress across the semiconductors are indicated.
Simulations for the steady-state are shown. A method to calculate the transfer functions is proposed and one
transfer function for type 1 is shown as an example. The inrush current, when the converter is connected to a
stiff input voltage source, is studied with the help of calculations, and time- and phase-diagrams. Several
variations and combinations are also shown.
Key-Words: - DC/DC converter, reduced duty cycle, step-up, step-down, step-up-down, inrush current
Received: May 11, 2024. Revised: September 14, 2024. Accepted: November 13, 2024. Published: December 23, 2024.
1 Introduction
DC/DC converters are important building blocks in
industrial and domestic systems. In addition to the
converters described in the textbooks, [1], [2], [3],
many other converters have been published. [4], is a
comprehensive review concerning step-up
converters. In the paper [5] more than a hundred
topologies are shown. The original study for
the generation and analyses of DC/DC converters is
[6]. For three terminal converters [7] is very
informative. A basic text concerning DC/DC
converters with limited duty cycle range is given in
[8]. The duty cycle ratio is lower or higher than one-
half. This can be interesting when snubber networks
are used where the recovery time is fixed, or when
the interleave concept is used. In these cases, two or
more converters are used in parallel and supplied
from the same input source feeding the same load.
The control signals are shifted by 180 degrees when
two converter stages are used or 120 degrees when
three stages are used. A second concept to combine
two converters is the floating two-stage converter,
[9], [10]. For this kind of converter, the now treated
converters can be used for the second stage.
2 Step-down Converters
Two versions of step-down converters are possible
(Figure 1 and Figure 3). Both converters are non-
inverting. To demonstrate the method of the
analyzation the converter type 1 is used.
Fig. 1: Type 1: step-down converter I
With ideal devices and continuous mode, one
has to describe the circuit with state equations for
the two modes, combine them, and linearize them to
get the operating point connections and the small
signal model. For mode M1, the active switch (the
transistor which can be turned on and off,
arbitrarily) is turned on, and the passive switch (the
diode) is off, one gets the state equations, a set of
differential equations:
1
12
1L
uu
dt
di C
L
(1)
2
21
2L
uu
dt
di CC
L
(2)
1
2
1C
i
dt
du L
C
(3)
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Felix A. Himmelstoss
E-ISSN: 2224-266X
239
Volume 23, 2024
. (4)
Now one can combine these four equations into one
matrix equation:
1
1
2
1
2
1
222
1
22
1
2
1
2
1
0
0
0
1
1
0
11
00
1
0
11
00
1
000
u
L
u
u
i
i
RCCC
C
LL
L
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
. (5)
For the second mode, M2 (the electronic switch is
off and the diode is on) the state equations are:
1
1
1L
u
dt
di C
L
(6)
2
12 L
u
dt
diL
(7)
1
1
1C
i
dt
du L
C
(8)
2
22 /
C
Ru
dt
du CC
. (9)
Combination leads to:
1
2
2
1
2
1
2
1
1
2
1
2
1
0
0
1
0
1
000
000
1
0000
0
1
00
u
L
u
u
i
i
RC
C
L
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
. (10)
When the time constants of the system are large
compared to the period of the switching frequency,
(5) is multiplied by d and (10) by (1-d) and both are
added to obtain the state space model of the
converter:
1
2
1
2
1
2
1
222
11
22
11
2
1
2
1
0
0
1
1
0
00
1
00
1
00
u
L
dL
d
u
u
i
i
RCC
d
C
dC
d
C
dL
d
L
dL
d
L
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
.
(11)
This model is also called a large signal model
because it is valid as long the converter does not
change into the discontinuous mode. The duty cycle
is also variable and is multiplied with the state
variables iL1, iL2, uC1, and uC2 and also with the input
variable u1. The large signal model is therefore a
nonlinear one. To obtain the transfer functions (c.f.
section 5) one has to linearize the equation around
an operating point. All variables can be described by
a combination of the operating point value (written
in capital letters with a zero in the index) and the
disturbance around the operating point (written with
small letters with a roof on top). The small signal
model is therefore:
d
u
C
II C
II L
UUU
L
DL
UUU
L
D
u
u
i
i
RCC
D
C
DC
D
C
DL
D
L
DL
D
L
D
u
u
i
i
dt
d
LL
LL
CC
CC
C
C
L
L
C
C
L
L
1
2
2010
1
2010
2
102010
2
0
1
102010
1
0
2
1
2
1
22
0
2
0
1
0
1
0
2
0
2
0
1
0
1
0
2
1
2
1
0
0
1
1
0
00
1
00
1
00
. (12)
For the operating point, one gets:
01 100200100 UDUDUD CC
(13)
01 100200100 UDUDUD CC
(14)
01 200100 LL IDID
(15)
0
200100 LOADLL IIDID
. (16)
This leads to the connections of the operating point
values according to:
1
10
10
U
UC
(17)
0
0
10
20 12
D
D
U
UC
(18)
1
10
LOAD
L
I
I
(19)
0
020 1
D
D
I
I
LOAD
L
. (20)
From (18) one can see that the duty cycle must be:
5.0
0D
. (21)
The steady-state voltage across C1 is equal to
the input voltage. This can be easily obtained by
inspecting the circuit diagram and looking at the
loop: input voltage U1, coil L2, capacitor C1, coil L1.
The voltages across the coils are zero in the mean,
and therefore the mean voltage across the capacitor
C1 must be equal to the input voltage. The mean
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Felix A. Himmelstoss
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240
Volume 23, 2024
current through the first inductor is equal to the load
current. From the voltage across the output capacitor
C2 one can see that the duty cycle is limited to
values greater than 0.5.
The voltage stress across the semiconductors is
given by:
max,12112max, 2DCS UUUUUUU
. (22)
Figure 2 shows a simulation for the steady state:
the currents through the coils, the load current, the
control signal, the output voltage, and the input
voltage. In the simulations of all converters
described in this paper, the inductors have the value
47 µH and the capacitors 330 µF.
Fig. 2: Type 1 up to down: current through L1 (red),
load current (brown), current through L2 (violet);
control signal (turquoise), output voltage (green),
input voltage (blue)
The second possible step-down converter with
a reduced duty cycle is shown in Figure 3.
Fig. 3: Type 2: step-down converter II
Just so as shown for type 1 one gets:
1
2
1
2
1
2
1
22
11
22
1
2
1
2
1
0
0
1
1
0
1
0
00
1
11
00
000
u
L
d
L
d
u
u
i
i
RCC
C
d
C
dLL
dL
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
(23)
d
u
C
II L
UU
L
DL
UU
L
D
u
u
i
i
RCC
C
D
C
DLL
DL
D
u
u
i
i
dt
d
LL
C
C
C
C
L
L
C
C
L
L
1
1
2010
2
1010
2
0
1
1010
1
0
2
1
2
1
22
1
0
1
0
22
0
1
0
2
1
2
1
00
0
1
1
0
1
0
00
1
11
00
000
. (24)
The operating point values are equal to those of
type 1 (17), (18), (19), (20), but the dynamics have
changed and so has the inrush current (cf. section 6).
The voltage stress across the semiconductors is
equal to the one of type 1.
3 Step-up Converters
It is also possible to construct two step-up
converters (Figure 4 and Figure 6) with reduced
duty cycle and ground on the positive input side.
Both converters are non-inverting, which means that
input and output voltages have the same polarity.
Fig. 4: Type 3, step-up converter I
With the help of Figure 4 one can immediately
see that the voltage across C1 must be equal to the
output voltage. The basic results are:
1
2
1
2
1
2
1
222
11
22
11
2
1
2
1
0
0
1
1
1
0
1
00
1
1
00
1
00
u
L
d
L
d
u
u
i
i
RCC
d
C
dC
d
C
dL
d
L
dL
d
L
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
(25)
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Felix A. Himmelstoss
E-ISSN: 2224-266X
241
Volume 23, 2024
d
u
C
II C
II L
UUU
L
DL
UUU
L
D
u
u
i
i
RCC
D
C
DC
D
C
DL
D
L
DL
D
L
D
u
u
i
i
dt
d
LL
LL
CC
CC
C
C
L
L
C
C
L
L
1
2
2010
1
2010
2
102010
2
0
1
102010
1
0
2
1
2
1
22
0
2
0
1
0
1
0
2
0
2
0
1
0
1
0
2
1
2
1
0
0
1
1
1
0
1
00
1
1
00
1
00
(26)
0
0
10
20
10
10
21
1
D
D
U
U
U
UCC
(27)
0
010
21
1
D
D
I
I
LOAD
L
(28)
0
020
21 D
D
I
I
LOAD
L
. (29)
By (27), (28), and (29) one can recognize that
the duty cycle must be lower than 0.5
5.0
0D
.
The converter must be driven by a duty cycle
smaller than one-half. The voltage stress across the
semiconductors is given by:
max,12211max, 2DCS UUUUUUU
. (30)
Figure 5 shows the currents through the
capacitors, the currents through the inductors, the
load current, the control signal, the input voltage,
and the output voltage.
Fig. 5: Type 3, up to down: current through C2
(dark violet); current through C1 (grey); current
through L1 (red), current through L2 (violet), load
current (brown); control signal (turquoise), input
voltage (blue), output voltage (green)
The second variant of a step-up converter is
shown in Figure 6. One can see that this converter
has a continuous input current because of the
inductor L1 and that the output voltage is the sum of
the input voltage and the voltage across C1.
Fig. 6: Type 4, step-up converter II
The basic results are:
1
1
2
1
2
1
222
11
22
11
2
1
2
1
0
0
0
1
1
0
1
00
1
1
00
1
00
u
L
u
u
i
i
RCC
d
C
dC
d
C
dL
d
L
dL
d
L
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
. (31)
Matrix A is equal to type 3 but the input matrix is
different. The small signal model is described by:
d
u
C
II C
II L
UU L
UU
L
u
u
i
i
RCC
D
C
DC
D
C
DL
D
L
DL
D
L
D
u
u
i
i
dt
d
LL
LL
CC
CC
C
C
L
L
C
C
L
L
1
2
2010
1
2010
2
2010
1
2010
1
2
1
2
1
22
0
2
0
1
0
1
0
2
0
2
0
1
0
1
0
2
1
2
1
0
0
0
1
1
0
1
00
1
1
00
1
00
. (32)
The operating point values differ compared to
the other type, but the converter has the same
voltage transformation ratio. The voltage across C1
changes according to:
0
0
10
10
21 D
D
U
UC
, (33)
the other values can be taken from (27), (28), (29).
The voltage stress across the semiconductors is
equal to the one of type 3.
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242
Volume 23, 2024
4 Step-up-down Converters
Four different step-up-down converters can be
constructed. All four are inverting the input voltage.
They have two distinct voltage transformation
ratios. The circuit diagram for type 5 is depicted in
Figure 7.
Fig. 7: Type 5, step-up-down converter I
The results were obtained in the same way as was
shown for type 1 and are:
1
2
1
2
1
2
1
22
11
22
1
2
1
2
1
0
0
1
1
0
1
0
00
1
1
00
0
1
00
u
L
dL
d
u
u
i
i
RCC
C
d
C
dLL
d
L
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
(34)
The small signal model has two input variables, the
input voltage and the duty cycle:
d
u
C
II L
UU
L
DL
UU
L
D
u
u
i
i
RCC
C
D
C
DLL
D
L
D
u
u
i
i
dt
d
LL
C
C
C
C
L
L
C
C
L
L
1
1
2010
2
1010
2
0
1
1010
1
0
2
1
2
1
22
1
0
1
0
22
0
1
0
2
1
2
1
00
0
1
1
0
1
0
00
1
1
00
0
1
00
. (35)
0
0
10
10
1D
D
U
UC
(36)
0
0
10
20
1
12
D
D
U
UC
(37)
0
010
1D
D
I
I
LOAD
L
(38)
1
20
LOAD
L
I
I
(39)
The duty cycle must be equal to or higher than 0.5:
5.0
0D
(40)
The voltage stress across the semiconductors is
given by:
max,2111max, 2DCS UUUUUU
(41)
Figure 8 depicts the input current, the currents
through the coils, the load current, the control
signal, and the input voltage. The input current is
negative during the off-time of the active switch. So
energy is fed back to the input source during this
off-time. One can interpret this as analogous to the
reactive power in an AC system.
Fig. 8: Type 5, up to down: input current (dark
violet); current through L1 (red), current through L2
(violet), load current (brown); output voltage
(green), control signal (turquoise), input voltage
(blue)
Figure 9 shows the second version with the
same voltage transformation ratio. The voltage
across C1 must be equal to the input voltage in the
steady state.
Fig. 9: Type 6, step-up-down converter II
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243
Volume 23, 2024
The results are:
1
2
1
2
1
2
1
222
11
22
11
2
1
2
1
0
0
1
1
0
11
00
1
11
00
1
00
u
L
d
L
d
u
u
i
i
RCC
d
C
dC
d
C
dL
d
L
dL
d
L
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
(42)
d
u
C
II C
II L
UUU
L
DL
UUU
L
D
u
u
i
i
RCC
D
C
DC
D
C
DL
D
L
DL
D
L
D
u
u
i
i
dt
d
LL
LL
CC
CC
C
C
L
L
C
C
L
L
1
2
2010
1
2010
2
102010
2
0
1
102010
1
0
2
1
2
1
22
0
2
0
1
0
1
0
2
0
2
0
1
0
1
0
2
1
2
1
0
0
1
1
0
11
00
1
11
00
1
00
(43)
1
10
10
U
UC
(44)
0
0
10
20
1
12
D
D
U
UC
(45)
1
10
LOAD
L
I
I
(46)
0
020
1D
D
I
I
LOAD
L
. (47)
From (45) one can recognize that the duty cycle
must be higher than 0.5:
5.0
0D
. (48)
The voltage stress across the semiconductors is
equal to the one of type 5.
The converter type 7 (Figure 10) has the
interesting quality that the input current is
continuous. The voltage across the first capacitor is
equal to the sum of the input and the output
voltages.
Fig. 10: Type 7, step-up-down converter III
The results are:
1
1
2
1
2
1
222
11
22
11
2
1
2
1
0
0
0
1
1
0
1
00
1
1
00
1
00
u
L
u
u
i
i
RCC
d
C
dC
d
C
dL
d
L
dL
d
L
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
(49)
d
u
C
II C
II L
UU L
UU
L
u
u
i
i
RCC
D
C
DC
D
C
DL
D
L
DL
D
L
D
u
u
i
i
dt
d
LL
LL
CC
CC
C
C
L
L
C
C
L
L
1
1
2010
1
2010
2
2010
1
2010
1
2
1
2
1
22
0
2
0
1
0
1
0
2
0
2
0
1
0
1
0
2
1
2
1
0
0
0
1
1
0
1
00
1
1
00
1
00
(50)
0
0
10
10
21
1
D
D
U
UC
(51)
0
0
10
20
21 D
D
U
UC
(52)
0
010
21 D
D
I
I
LOAD
L
(53)
0
020
21
1
D
D
I
I
LOAD
L
. (54)
From the steady-state equations one can see that the
duty cycle must be lower than 0.5:
5.0
0D
. (55)
The duty cycle must be smaller than 0.5.
Figure 11 depicts the current through the inductors,
WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS
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Felix A. Himmelstoss
E-ISSN: 2224-266X
244
Volume 23, 2024
the load current, the output voltage, the control
signal, and the input voltage. The voltage stress
across the semiconductors is given by
max,2112max, 2DCS UUUUUU
. (56)
Figure 11; Type 7, up to down: current through L2
(violet), current through L1 (red), load current
(brown); output voltage (green), control signal
(turquoise), input voltage (blue)
Figure 12 shows the fourth possibility to design
a step-up-down converter with a reduced duty cycle.
Fig. 12: Type 8, step-up-down converter IV
The linearized model is:
d
u
C
II C
II L
UUU
L
DL
UUU
L
D
u
u
i
i
RCC
D
C
DC
D
C
DL
D
L
DL
D
L
D
u
u
i
i
dt
d
LL
LL
CC
CC
C
C
L
L
C
C
L
L
1
2
2010
1
2010
2
102010
2
0
1
102010
1
0
2
1
2
1
22
0
2
0
1
0
1
0
2
0
2
0
1
0
1
0
2
1
2
1
0
0
1
0
1
00
1
1
00
1
00
. (57)
The large signal model is given by:
1
2
1
2
1
2
1
222
11
22
11
2
1
2
1
0
0
1
0
1
00
1
1
00
1
00
u
L
d
L
d
u
u
i
i
RCC
d
C
dC
d
C
dL
d
L
dL
d
L
d
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
(58)
The state matrix is equal to the one for type 7.
The connections between the operating point values
are equal to those of type 7 except:
0
0
10
10
21 D
D
U
UC
. (59)
The voltage stress across the semiconductors is
equal to the one of type 5.
Figure 13 shows the input current, the current
through the coils, the load current, the output
voltage, the control signal, and the input voltage.
The input current is pulsating.
Fig. 13: Type 8, up to down: input current (dark
violet); current through L2 (violet), current through
L1 (red), load current (brown); output voltage
(green), control signal (turquoise), input voltage
(blue)
5 Transfer Function
Using the simple linear control theory, the transfer
functions of the converter must be known. Utilizing
abbreviations for the elements of the state matrix
and the input matrix:
d
u
B
B
BB
BB
u
u
i
i
AAA
AA
AA
AA
u
u
i
i
dt
d
C
C
L
L
C
C
L
L
1
42
32
2221
1211
2
1
2
1
444241
3231
2423
1413
2
1
2
1
0
0
0
00
00
00
(60)
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and with the Laplace transformation:
)(
)(
0
0
)(
)(
)(
)(
0
0
0
0
1
42
32
2221
1211
2
1
2
1
444241
3231
2423
1413
sD
sU
B
B
BB
BB
sU
sU
sI
sI
AsAA
sAA
AAs
AAs
C
C
L
L
.
(61)
One can calculate eight transfer functions.
The denominator of all these transfer functions
is the determinant of the coefficient matrix and is
given by:
)62(.
413223144132241342312314
423124133223311344
2
3223311342244114
3
44
4
AAAAAAAAAAAA
AAAAsAAAAA
sAAAAAAAAsAsDen
The most important numerators are the voltage
across the second capacitor (which is the output
voltage) in dependence on the duty cycle and on the
input voltage. The transfer functions are given by:
DEN
DNUMU
sG DU 2
)(
2
(63)
DEN
UNUMU
sG UU 12
)(
12
(64)
with
)
(
NUMU2D
1241322312423123
2241311322423113
324113324223423113
423223
2
12412242
3
42
BAAABAAA
BAAABAAA
s
BAABAABAA
BAA
sBABAsB
(65)
1141322311423123
1241321312423113
2
11411242
UMU2U1
BAAABAAA
BAAABAAA
sBABAN
. (66)
Figure 14 shows the Bode plot between the
output voltage and the duty cycle, of a converter of
type 1. One can see the two resonances caused by
the two conjugate complex pole pairs and a complex
zero which must have a positive real part because
these zeros also shift the phase by minus 180
degrees. The third zero has a negative real part and
shifts the phase up again by 90 degrees.
Fig. 14: Bode plot between output voltage and duty
cycle: solid line: gain, dotted line: phase
6 Inrush Current
A very important topic is the inrush current when
the converter is connected to a stable input voltage
source such as batteries or a stiff DC grid. In this
section, the basics are described. The inductors are
taken as constant. In practice, they will probably
saturate and their value will decrease. The inrush
current will therefore be higher. For the calculation,
the saturated inductor value can be used in this case.
6.1 Type 1 (Figure 1)
The output is decoupled by the switch. The inrush
current is described by:
t
IN
IN dti
Cdt
di
LLU 0
1
211
1
(67)
Leading to an inrush current of the undamped
resonant circuit:
t
LLCLL
C
UiIN
21121
1
1
1
sin
. (68)
Due to parasitic resistors, this ringing is damped
and is shown as a diagram with the voltage across
C1 in the horizontal direction and with the current
through both inductors in the vertical direction
(Figure 15). The final value of the voltage across C1
is equal to the input voltage and the currents through
the coils are zero.
Fig. 15: Type 1: inrush
6.2 Type 2 (Figure 3)
The resonant circuit which produces the inrush
consists of the series connection of the two coils and
the two capacitors and is described by:
t
IN
IN dti
CC
CC
dt
di
LLU 0
21
21
211
(69)
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Leading to:
t
LLCC
CC
CCLL
CC
UiIN
2121
21
2121
21
1sin
. (70)
Figure 16 shows the damped inrush current.
Fig. 16: Type 2: inrush current
6.3 Type 3 (Figure 4)
The diode allows only one half-period of the inrush
current. A small ringing occurs between the
inductors and the capacitors, but this does not
influence the input source. Figure 17 shows the
currents through the diode and the coils.
Fig. 17: Type 3, up to down: input current (red),
current through L1 (blue), current through L2
(green)
The calculation of the inrush peak through the
diode is very simple. With constant input voltage
U1 connected to the circuit, two currents through
the two series-resonant circuits occur. For the
current of the first resonant circuit, one can use the
differential-integral equation:
t
L
Ldti
Cdt
di
LU 02
1
2
21
1
(71)
Leading to:
t
LCL
C
UiL
212
1
12
1
sin
. (72)
A similar equation can be written for the second
resonance circuit (L1, C2) leading to a current peak
of
1
2
2
1
1L
C
L
C
UI IN
. (73)
6.4 Type 4 (Figure 6)
When the input voltage is applied to the converter,
D1 turns on and during this time the inrush current,
which is equal to the current through L1, is
described only by:
t
L
Ldti
Cdt
di
LU 01
2
1
11
1
(74)
Leading to:
t
LCL
C
UiL
121
2
12
1
sin
. (75)
This equation is only valid as long as the diode
is conducting. The characteristic impedance of the
resonant circuit Z=0.378 Ω leads to the inrush peak
value:
A64
1
LIN II
. (76)
The peak value of the simulation is a little bit
lower because of the parasitic resistors and due to a
small current through C1 and L2 because of the
onward voltage of the diode.
Approximately, after a one-half period the diode
turns off and both capacitors and both coils are in
series. Now the inrush current is described by (the
load resistor is omitted):
t
IN
IN dti
CC
CC
dt
di
LLU 0
21
21
211
(77)
Leading to:
t
LLCC
CC
CCLL
CC
UiIN
2121
21
2121
21
1sin
. (78)
The characteristic impedance is reduced to:
21
2121 CC
CCLL
Z
(79)
Leading to:
Z=0.75 Ω,
A32
IN
I
, ω=8030 s-1, f=1278 Hz, T=783 µs
The damping is produced by the parasitic resistors
and the applied load.
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Fig. 18: Type 4, up to down: current through the
diode (dark violet); inrush current (red)
Fig. 19: Type 4, inrush current (red) drawn over the
output voltage
With the help of a phase diagram (Figure 19),
the complete inrush is depicted.
Figure 18 shows the current through D1 and the
current through L1 which is equal to the inrush
current at the beginning.
6.5 Type 5 (Figure 7)
The inrush current which is equal to the current
through L1 is described by:
t
IN
IN dti
CC
CC
dt
di
LLU 0
21
21
211
(80)
Leading to:
t
LLCC
CC
CCLL
CC
UiIN
2121
21
2121
21
1sin
. (81)
The output voltage and the inrush current after
turning on are shown in Figure 20 and also a phase
diagram between these two signals is given in
Figure 21. The final value is zero for both variables.
Fig. 20: Type 5, up to down: output voltage (green),
input voltage (blue); inrush current (red)
Fig. 21: Type 5, inrush current (red) drawn over the
output voltage
6.6 Type 6 (Figure 9)
The output is decoupled by the diode. The inrush
current is described by:
t
IN
IN dti
Cdt
di
LLU 0
1
211
1
(82)
Leading to:
t
LLCLL
C
UiIN
21121
1
1
1
sin
. (83)
In Figure 22 the inrush current and the input and
output voltages are shown. There is no influence on
the output (and therefore across the load).
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Fig. 22: Type 6, up to down: inrush current (dark
violet); output voltage (green), input voltage (blue)
6.7 Type 7 (Figure 10)
When the input voltage is applied to the converter,
D1 turns on and at the beginning, the inrush current,
which is equal to the current through L1, is
described only by:
t
L
Ldti
Cdt
di
LU 01
1
1
11
1
(84)
Leading to:
t
LCL
C
UiL
121
2
12
1
sin
. (85)
This equation is only valid as long as the diode
is conducting. The characteristic impedance of the
resonant circuit Z=0.378 Ω leads to the inrush peak
value
A64
1
LIN II
.
The peak value of the simulation is a little bit
lower because of the parasitic resistors and a small
current through C2 and L2 and due to the onward
voltage of the diode.
Approximately, after a one-half period the diode
turns off and both capacitors and both coils are in
series. Now the inrush current is described by (the
load resistor is omitted)L
t
IN
IN dti
CC
CC
dt
di
LLU 0
21
21
211
(86)
Leading to:
t
LLCC
CC
CCLL
CC
UiIN
2121
21
2121
21
1sin
. (87)
The characteristic impedance is changed to:
21
2121 CC
CCLL
Z
. (88)
The damping is produced by the parasitic
resistors and the applied load. The phase diagram
current through L1, which is equal to the inrush
current over the output voltage is shown in
Figure 23.
Fig. 23: Type 7, inrush current (red) drawn over the
output voltage
6.8 Type 8 (Figure 12)
No inrush can occur because of the position of the
electronic switch.
7 Further Modifications
7.1 Floating Two-Stage Converters
The concept is shown for type 1. The converter type
1 (Figure 1) is combined with another converter,
where the reference is the negative input terminal
(Figure 24). The control signals are shifted by 180
degrees.
Fig. 24: Two-stage floating converter with limited
duty cycle type 1
Figure 25 shows the input current, the currents
through the coils L12 and L22 of stage 2, the
currents through the coils L11 and L21 of stage 1,
the input voltage, the voltage across one output
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capacitor, the control signal of S2, the output
voltage, and the control signal of S1. The frequency
of the input current is doubled.
Fig. 25: Two-stage floating converter with limited
duty cycle type 1: up to down: input current (dark
violet); currents through the coils of stage 2 L12
(grey), L22 (light brown); currents through the coils
of stage 1 L11 (red), L21 (violet); input voltage
(blue), voltage across output capacitor (dark blue),
control signal of S2 (dark green, shifted), output
voltage (green), control signal of S1 (turquoise)
7.2 Interleaved Converter
As an example, two converters according to type 1
are combined. The circuit diagram is given in
Figure 26.
Fig. 26: Two-stage interleaved converter with
limited duty cycle type 1
The inputs and the outputs of the converters are
connected in parallel. This concept is useful for
higher-power applications. When the control signals
of the two stages are shifted by 180 degrees, the
input frequency is doubled. When three converters
are used in parallel, the control signals have to be
shifted by 120o. Using n converter stages the control
signals are shifted by 360o/n. The input current is
smoothed. For partial load, not all converters have
to be in operation and those used will work with
higher efficiency.
Figure 27 shows the input current, the currents
through the coils of stage 2 L12 and L22, the
currents through the coils of stage 1 L11 and L21,
the control signal of S2, the control signal of S1, the
output voltage, and the input voltage.
Fig. 27: Two-stage interleaved converter with
limited duty cycle type 1, up to down: input current
(dark violet); currents through the coils of stage 2
L12 (light brown), L22 (grey); currents through the
coils of stage 1 L11 (red), L21 (violet); control
signal of S2 (dark green, shifted), control signal of
S1 (turquoise), output voltage (green), input voltage
(blue)
7.3 Modified Converter
Other interesting converters can be found when the
position of the output capacitor is changed and
connected between input and output. This is again
shown for the converter type 1 in Figure 28.
Fig. 28: Modified limited duty cycle converter
type 1
The input current is now continuous, the voltage
stress across the capacitor is changed, and the inrush
current is also modified.
8 Conclusion
Eight DC/DC converters were investigated. Two of
them are step-down, two of them are step-up, and
four of them are step-up-down converters. All of
them have the following features:
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Felix A. Himmelstoss
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The reference is the positive input voltage
terminal
The duty cycle is larger or smaller than one-
half
They can be combined to form interleaved
converters
Other interesting features can be found:
Continuous input current (type 4, 7)
No inrush current (type 8)
Input current with small energy feedback
phases (type 1, 2, 5, and 6)
Pulsed input current (type 3, 8)
Continuous output current (type 2, 5)
The converters are useful when the reference
point must be positive. This is typical of
communication circuits and of electrochemical
applications. The converters can easily be combined
with another converter, where the reference is the
negative input terminal to form a floating two-stage
converter. The combination of two or more
converters to form interleaved converters are also an
interesting application.
References:
[1] F. Zach, Leistungselektronik, Frankfurt:
Springer, 6th edition 2022 (Text in German).
[2] N. Mohan, T.Undeland, & W. Robbins,
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and Design, New York: W. P. John Wiley &
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[3] Y. Rozanov, S. Ryvkin, E. Chaplygin, P.
Voronin, Power Electronics Basics, CRC
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Blaabjerg, and B. Lehman, Step-Up DC–DC
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10.1109/TPEL.2017.2652318.
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Contribution of Individual Authors to the
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Policy)
The author contributed to the present research, in all
stages from the formulation of the problem to the
final findings and solution.
Sources of Funding for Research Presented in a
Scientific Article or Scientific Article Itself
No funding was received for conducting this study.
Conflict of Interest
The author has no conflicts of interest to declare.
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(Attribution 4.0 International, CC BY 4.0)
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WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS
DOI: 10.37394/23201.2024.23.24
Felix A. Himmelstoss
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Volume 23, 2024