A Novel Hybrid PWM Technique for Asymmetric Inverter

LAKSHMI PRASANNA, T. R. JYOTHSNA

Department of Electrical Engineering,

Andhra University,

Visakhapatnam,

INDIA

Abstract: - Multi-Level Inverters (MLIs) are achieving broad popularity owing to the rapid development of

switching and conduction power losses. In this work, the proposed PWM scheme is employed for asymmetric

multilevel inverter. The proposed configuration is also examined using PLECS software to estimate losses and

efficiency. The simulation work is done in the MATLAB/Simulink environment and the OPAL-RT(OP4510)

test platform is employed to evaluate topology performance.

Key-Words: - Hybrid PWM, Multi-level Inverter, Total Harmonic Distortion, DC-AC conversion, Total

Standing Voltage, OPAL-RT(OP4510).

Received: February 19, 2023. Revised: November 27, 2023. Accepted: December 14, 2023. Published: December 31, 2023.

The traditional two-level inverter is inadequate for

implementation in the applications as mentioned

earlier for several unanticipated limitations like

higher harmonic distortion, less efficiency, reduced

power quality, and so on. Considering these

scenarios, MLIs have proven to serve as a viable

substitute for an extensive range of purposes,

[1],[2].

like Neutral Point Clamped MLI (NPCMLI), Flying

are transitioning from a traditional perspective to

real-world applications due to capabilities that

include high degree of modularity, and the ability to

safely link to medium voltage with superior power

quality, [5].

counts for electric vehicle applications are

suggested, [15]. In [16], author recommends a

unique eleven level inverter utilizing reduced

switches, minimizing control complexity and cost

reduction. Analysis of various modulation schemes

switching and dc sources is proposed, and the

results are evaluated, [19]. To address the

challenges associated with the nine-level inverter, a

seventeen-level MLI was proposed and executed, as

well as increasing the number of levels without the

impact of component ratings, [20]. A comparison of

various PV-inverter topologies is simulated to

minimize leakage current variation, [21]. Packed E-

cell configuration utilizing nearest level modulation

for PV applications is investigated through OPAL-

balancing ability, [25]. A novel MLI structure is

developed utilizing unidirectional and bidirectional

switches, [26].

Figure 1. Modulation techniques are categorized as

High Frequency Scheme (HFS) or Low Frequency

Scheme (LFS) based on the frequency of the carrier.

LSPWM and PSPWM techniques are HFS methods

typically recommended for medium-voltage

applications. In contrast to PSPWM, LSPWM

asymmetric. Those are (i) equal voltage cascaded

MLI(ECHBMLI), where all input voltages are in

equal magnitude, (ii)natural sequence cascaded

MLI(NSCHBMLI), where all input voltage follows

arithmetic progression each is differed by one, (iii)

binary cascaded MLI(BCHBMLI), where

successive input voltages are doubled,(iv)trinary

cascaded MLI(TCHBMLI), in which successive

PLSPWM has been successful, which is simple

open-loop system that is tested through the

OPAL-RT simulator.

(g). V0=0Vin (h). V0=-1Vin

Fig. 3: Operating Modes of Topology

S2, S5, S6, S9, and S10 create conduction path to link

the source with load as depicted in Figure 3(a). In

the same fashion -5Vin appears across the load by

turning on switches S3, S4, S7, S8, S11, and S12

respectively as illustrated in Figure 3(l).

+1Vin as voltage level. To get -1Vin as voltage level,

the path of conduction is given in Figure 3(h).

mode of operation, either S1, S3, S6, S8, S9, and S11

conduct or S2, S4, S5, S7, S10, and S12 conduct, as

Figure 4 indicates the LSPWM scheme and

proposed PLSPWM scheme. For both the cases

reference wave amplitude and frequency are Aref and

it demands ten carriers and one reference to send

gating pulses to switches. For LSPWM modulation

index (ma) is represented as

(1)

where Aref and Acarrier are amplitudes of reference

and carrier respectively. In LSPWM, ten carriers

formed by keeping an equal magnitude of Acarrier

with each other and level shifted. Like LSPWM, for

PLSPWM the magnitude of the output is decided by

using modulation index (ma), which is indicated as

(2)

(7)

comparison aspects are the number of switches,

drivers, diodes, capacitors required, DC sources,

applied PWM method, operating value of carrier

frequency, and type of configuration. In [13], the

authors utilize asymmetric configuration with fewer

switches and the same carrier frequency as proposed

topology however it is a symmetric configuration,

requires six sources and the operation scheme is

Level Shifted Pulse Width Modulation (LSPWM).

In [22], authors use a symmetric configuration, a

minimal number of switches contrasted to the

proposed topology but it requires capacitors. So,

voltage balancing plays a vital role in the design of

configuration. In [14], it requires the same switch

proposed topology yields sophisticated results.

Table 3. Simulating Parameters

5 Results and Discussions

resistance and 100mH for inductance. The

frequency at which it operates of the suggested

inverter is the fundamental frequency(50Hz). The

functioning of the inverter according to R-load can

be seen in Figure 7. The output current seems to be

proposed topology appears to be suitable for high-

frequency performing appliances.