A Novel Hybrid PWM Technique for Asymmetric Inverter

af9da9b5-6234-4b9c-a940-56085f64e91320240215050248003wseas:wseasmdt@crossref.orgMDT DepositWSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS2224-266X1109-273410.37394/23201http://wseas.org/wseas/cms.action?id=28612720232720232210.37394/23201.2023.22https://wseas.com/journals/cas/2023.phpA Novel Hybrid PWM Technique for Asymmetric InverterLakshmiPrasannaDepartment of Electrical Engineering, Andhra University, Visakhapatnam, INDIAT. R.JyothsnaDepartment of Electrical Engineering, Andhra University, Visakhapatnam, INDIAMulti-Level Inverters (MLIs) are achieving broad popularity owing to the rapid development of power semiconductor devices. The capability of MLIs became recognized as a significant aspect of a system heavily reliant on Pulse Width Modulation(PWM) strategy. The conventional high frequency PWM techniques suffer from significant Total Harmonic Distortion (THD) along with power loss difficulties. This work recommends a hybrid PWM technique for lowering the THD and power loss of VSI adding the benefits of level-shift PWM and Phase-shift PWM. A novel form of carrier signals is employed in the proposed hybrid PWM technique. In contrast to existing PWM techniques, the proposed hybrid PWM technique minimizes switching and conduction power losses. In this work, the proposed PWM scheme is employed for asymmetric multilevel inverter. The proposed configuration is also examined using PLECS software to estimate losses and efficiency. The simulation work is done in the MATLAB/Simulink environment and the OPAL-RT(OP4510) test platform is employed to evaluate topology performance.123120231231202323024225https://wseas.com/journals/cas/2023/a505101-810.pdf10.37394/23201.2023.22.25https://wseas.com/journals/cas/2023/a505101-810.pdf10.1109/tie.2002.801052J. Rodriguez, Jih-Sheng Lai and Fang Zheng Peng, "Multilevel inverters: a survey of topologies, controls, and applications," in IEEE Transactions on Industrial Electronics, vol. 49, no. 4, pp. 724-738, Aug. 2002, doi: 10.1109/TIE.2002.801052. 10.1109/tie.2010.2049719S. Kouro, Malinowski, Gopakumar.K, Josep Pou, L.G. Franquelo, BinWu, J. Rodriguez, Parez, Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2553–2580, Aug. 2010, doi: 10.1109/TIE.2010.2049719. 10.1049/iet-pel.2010.0027S. De, D. Banerjee, K. Siva Kumar, K. Gopakumar, R. Ramchand, and C. Patel, “Multilevel inverters for low-power application,” IET Power Electronics, vol. 4, no. 4, pp. 384–392, Apr. 2011, doi: 10.1049/iet-pel.2010.0027. 10.1109/tie.2010.2043039H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, “Medium-voltage multilevel converters State of the art, challenges, and requirements in Industrial applications,” IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2581–2596, Aug. 2010, doi: 10.1109/TIE.2010.2043039. 10.1109/tie.2009.2030767M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, “A survey on cascaded multilevel inverters,” IEEE Transactions on Industrial Electronics, vol. 57, no. 7. pp. 2197–2206, Jul. 2010. doi: 10.1109/TIE.2009.2030767. 10.1109/tpel.2015.2405012K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel inverter topologies with reduced device count: A review,” IEEE Transactions on Power Electronics, vol. 31, no. 1. Institute of Electrical and Electronics Engineers Inc., pp. 135–151, Jan. 01, 2016. doi: 10.1109/TPEL.2015.2405012. 10.1109/access.2019.2913447P. R. Bana, K. P. Panda, R. T. Naayagi, P. Siano, and G. Panda, “Recently Developed Reduced Switch Multilevel Inverter for Renewable Energy Integration and Drives Application: Topologies, Comprehensive Analysis and Comparative Evaluation,” IEEE Access, vol. 7, pp. 54888–54909, 2019, doi: 10.1109/ACCESS.2019.2913447. 10.1109/ojies.2021.3050214H. P. Vemuganti, D. Sreenivasa Rao, S. K. Ganjikunta, H. M. Suryawanshi, and H. AbuRub, “A survey on reduced switch count multilevel inverters,” IEEE Open Journal of the Industrial Electronics Society, vol. 2, pp. 80–111, 2021, doi: 10.1109/OJIES.2021.3050214. 10.1109/access.2020.2969551P. Omer, J. Kumar, and B. S. Surjan, "A Review on Reduced Switch Count Multilevel Inverter Topologies", IEEE Access, vol. 8, pp. 22281-22302, 2020. Prathiba T, Renuga P, “Performance analysis of symmetrical and asymmetrical cascaded H-bridge inverter,” Int. J. Electrical Eng., 2013;13(2):32–38. 10.1049/iet-pel.2016.0283Prabaharan N, Palanisamy K, “Comparative analysis of symmetric and asymmetric reduced switch MLI topologies using unipolar pulse width modulation strategies,” IET Power Electron., 2016, 9(15), pp.2808– 2823. 10.11591/ijpeds.v7.i3.pp854-862Periyaazhagar D, Irusapparajan G. “Asymmetrical cascaded multi-level inverter using control freedom pulse width modulation techniques,” Int J Power Electron Drive Sys. 2016; 7:848–856. 10.1002/2050-7038.12191M. D. Siddique, S. Mekhilef, N. M. Shah, A. Sarwar, and M. A. Memon, "A new singlephase cascaded multilevel inverter topology with a reduced number of switches and voltage stress", Int. Trans. Electr. Energy Syst., vol. 30, no. 2, pp. 1-21, 2020. 10.1109/resem57584.2023.10236127P. Gawhade, A. Narwaria, A. Raghuvanshi, A. Ojha, "A New Basic Module based Reduced Switch Cascaded Multilevel Inverter," 2023 IEEE Renewable Energy and Sustainable E-Mobility Conference (RESEM), Bhopal, India, 2023, pp. 1-5, doi: 10.1109/RESEM57584.2023.10236127. 10.1109/sceecs57921.2023.10062982V. Kumar, P. Kumari, and N. Kumar, "Comparison of different levels of cascaded H bridge multilevel inverter using PSPWM technique for EV applications," 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS), Bhopal, India, 2023, pp. 1-8, doi: 10.1109/SCEECS57921.2023.10062982. 10.1109/isgt-asia.2018.8467799R. Girish Ganesan, M. Bhaskar, and K. Narayanan, "Novel 11-level Multi-level Inverter", 2018 IEEE Innovative Smart Grid Technologies - Asia (ISGT Asia), pp. 1050- 1055, 2018. Sahu.M. K, M. Biswal, Jena, R. K., & Malla. J. M. R. ‘’Simulation of different levels of multilevel inverter using Cascaded H-Bridge for various loads’’ TEST Engineering & Management, 83(May-June 2020), 7527- 7535. 10.1088/1755-1315/188/1/012039S. X. Zhou, Z. X. Sang, J. Zhang, L. Jing, Z. Du, and Q. T. Guo, “Comparison on modulation schemes for 15-level cascaded H-bridge multilevel inverter,” IOP Conf Ser Earth Environ Sci, vol. 188, p. 012039, Oct. 2018, doi: 10.1088/1755-1315/188/1/012039. 10.1088/1742-6596/1706/1/012092N. Vishwajith, S. Nagaraja Rao, and S. Sachin, “Performance analysis of reduced switch ladder type multilevel inverter using various modulation control strategies,” J Phys Conf Ser, vol. 1706, no. 1, p. 012092, Dec. 2020, doi: 10.1088/1742- 6596/1706/1/012092. 10.1088/1757-899x/981/4/042071B. Sathyavani and S. Tara Kalyani, “Implementation of LDN to MLI and RSCMLI configurations with a simple carrierbased modulation,” IOP Conf Ser Mater Sci Eng, vol. 981, no. 4, p. 042071, Dec. 2020, doi: 10.1088/1757-899X/981/4/042071. 10.1088/2631-8695/acf549M. A. Alam, S. V. A. V Prasad, and M. Asim, “Performance analysis of different transformer-less inverter topologies for gridconnected PV systems,” Engineering Research Express, vol. 5, no. 3, p. 035063, Sep. 2023, doi: 10.1088/2631-8695/acf549. 10.1016/j.prime.2023.100152Sanjay Upreti, Bhim Singh, Narendra Kumar,” A new three-phase eleven level packed e-cell converter for solar grid-tied applications’’, e-Prime - Advances in Electrical Engineering, Electronics and Energy, Vol. 4, 2023, 100152, https://doi.org/10.1016/j.prime.2023.100152. 10.1088/1757-899x/804/1/012049J. A. Lone and F. I. Bakhsh, “Design and Analysis of Cascaded H Bridge Nine-Level Inverter in Typhoon HIL,” IOP Conf Ser Mater Sci Eng, vol. 804, no. 1, p. 012049, Apr. 2020, doi: 10.1088/1757- 899X/804/1/012049. 10.1002/2050-7038.12587/v2/response1Z. Sarwer, M. D. Siddique, A. Iqbal, A. Sarwar, and S. Mekhilef, ‘‘An improved asymmetrical multilevel inverter topology with reduced semiconductor device count,’’ Int. Trans. Electr. Energy Syst., vol. 30, no. 11, p. e12587, Nov. 2020. 10.1109/tpel.2019.2963344M. N. H. Khan, M. Forouzesh, Y. P. Siwakoti, L. Li, and F. Blaabjerg, “Switched capacitor integrated (2n + 1)-level step-up single-phase inverter,” IEEE Trans. Power Electron., vol. 35, no. 8, pp. 8248–8260, Aug. 2020. 10.1109/tie.2016.2592460R. S. Alishah, S. H. Hosseini, E. Babaei, and M. Sabahi, “A new general multilevel converter topology based on the cascaded connection of sub multilevel units with reduced switching components, DC sources, and blocked voltage by switches,” IEEE Trans. Ind. Electron., vol. 63, no. 11, pp. 7157–7164, Nov. 2016.